DS3141 Maxim Integrated Products, DS3141 Datasheet - Page 56

• Manufacturer Part Number: DS3141
• Description: Network Controller & Processor ICs Single Ch DS3;-E3 Fr Framer T3-E3 Framer
• Manufacturer: Maxim Integrated Products

Specifications of DS3141

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 2.048 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 90 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: CSBGA

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 2 to 0: Transmit Low Watermark Select Bits (TLWMS[2:0]). These control bits determine when the HDLC
controller should set the TLWM status bit in the
number of bytes specified by these bits, the TLWM status bit is set to logic 1.
Bits 4 to 6: Receive High Watermark Select Bits (RHWMS[2:0]). These control bits determine when the HDLC
controller should set the RHWM status bit in the
number of bytes specified by these bits, the RHWM status bit is set to logic 1.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 2: Transmit FIFO Low Watermark (TLWM). This real-time status bit is set to 1 when the transmit FIFO
contains less than the number of bytes configured by TLWMS[2:0] control bits in the
cleared when the FIFO fills beyond the low watermark.
Bit 3: Receive FIFO High Watermark (RHWM). This real-time status bit is set to 1 when the receive FIFO
contains more than the number of bytes configured by the RHWMS[2:0] control bits in the
cleared when the FIFO empties below the high watermark.
RHWMS[2:0]
TLWMS[2:0]
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
N/A
—
7
N/A
—
7
RHWMS2
TRANSMIT LOW WATERMARK (BYTES)
RECEIVE HIGH WATERMARK (BYTES)
6
0
N/A
—
6
HSR
HDLC Status Register
54h
HCR2
HDLC Control Register 2
51h
RHWMS1
N/A
112
144
176
208
240
112
144
176
208
240
5
0
—
16
48
80
16
48
80
5
RHWMS0
HSR
HSR
56 of 88
N/A
—
4
4
0
register. When the transmit FIFO contains less than the
register. When the receive FIFO contains more than the
N/A
RHWM
—
3
—
3
TLWMS2
2
0
TLWM
—
2
TLWMS1
HCR2
HCR2
1
0
N/A
—
1
register. This bit is
register. This bit is
TLWMS0
N/A
0
0
—
0