LAN89218AQ_samples SMSC, LAN89218AQ_samples Datasheet - Page 142
LAN89218AQ_samples
Manufacturer Part Number
LAN89218AQ_samples
Description
Ethernet ICs High Perform Chip 10/100 NonPCI Cntrl
Manufacturer
SMSC
Datasheet
1.LAN89218AQ.pdf
(155 pages)
Specifications of LAN89218AQ_samples
Ethernet Connection Type
10BASE-T, 100BASE-TX
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Product
Ethernet Controllers
Standard Supported
IEEE802.3, IEEE802.3u
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Operating Temperature
+ 85 C
Package / Case
TQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 142 of 155
- Download datasheet (3Mb)
Revision 1.3 (02-23-10)
6.7
A[2:1], END_SEL
SYMBOL
t
cycle
t
t
t
t
t
t
csh
asu
dsu
csl
ah
dh
FIFO_SEL
nCS, nWR
Data Bus
In this mode the upper address inputs are not decoded, and any write to the LAN89218 will write the
TX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a write access. This is
normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is
useful when the host processor must increment its address when accessing the LAN89218. Timing is
identical to a PIO write, and the FIFO_SEL signal has the same timing characteristics as the address
lines.
Timing for 16-bit and 32-bit cycles is identical with the exception that D[31:16] is ignored during a 16-
bit write. Note that address lines A[2:1] are still used when the LAN89218 is operating in 32-bit and
16-bit mode. Address bits A[7:3] are ignored.
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths.
Note: A TX Data FIFO Direct PIO Write cycle begins when both nCS and nWR are asserted. The
TX Data FIFO Direct PIO Writes
DESCRIPTION
Write Cycle Time
nCS, nWR Assertion Time
nCS, nWR Deassertion Time
Address, END_SEL, FIFO_SEL Setup to nCS, nWR
Assertion
Address, END_SEL, FIFO_SEL Hold Time
Data Setup to nCS, nWR Deassertion
Data Hold Time
cycle ends when either or both nCS and nWR are deasserted. They may be asserted and
deasserted in any order.
Figure 6.6 TX Data FIFO Direct PIO Write Timing
Table 6.8 TX Data FIFO Direct PIO Write Timing
t
asu
High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications
DATASHEET
142
t
csl
t
t
cycle
dsu
MIN
45
32
13
0
0
7
0
t
dh
t
ah
TYP
t
csh
MAX
SMSC LAN89218
Datasheet
UNITS
ns
ns
ns
ns
ns
ns
ns
Related parts for LAN89218AQ_samples
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
Ethernet ICs High Perform Chip 10/100 NonPCI Cntrl
Manufacturer:
SMSC
Datasheet:
Part Number:
Description:
FAST ETHERNET PHYSICAL LAYER DEVICE
Manufacturer:
SMSC Corporation
Datasheet:
Part Number:
Description:
357-036-542-201 CARDEDGE 36POS DL .156 BLK LOPRO
Manufacturer:
SMSC Corporation
Datasheet:
Part Number:
Description:
357-036-542-201 CARDEDGE 36POS DL .156 BLK LOPRO
Manufacturer:
SMSC Corporation
Datasheet:
Part Number:
Description:
357-036-542-201 CARDEDGE 36POS DL .156 BLK LOPRO
Manufacturer:
SMSC Corporation
Datasheet:
Part Number:
Description:
4-PORT USB2.0 HUB CONTROLLER
Manufacturer:
SMSC Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
SMSC Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
SMSC Corporation
Datasheet:
Part Number:
Description:
FDC37C672ENHANCED SUPER I/O CONTROLLER WITH FAST IR
Manufacturer:
SMSC Corporation
Datasheet:
Part Number:
Description:
COM90C66LJPARCNET Controller/Transceiver with AT Interface and On-Chip RAM
Manufacturer:
SMSC Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
SMSC Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
SMSC Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
SMSC Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
SMSC Corporation
Datasheet: