MT8888CE1 Zarlink, MT8888CE1 Datasheet - Page 5

• Manufacturer Part Number: MT8888CE1
• Description: DTMF TXRX 3.58MHz CMOS 5V 20-Pin PDIP Tube
• Manufacturer: Zarlink

Specifications of MT8888CE1

• Package: 20PDIP
• Operating Frequency: 3.58 MHz
• Typical Supply Current: 7 mA
• Typical Operating Supply Voltage: 5 V
• Minimum Operating Supply Voltage: 4.75 V
• Maximum Operating Supply Voltage: 5.25 V

Note: 0= LOGIC LOW, 1= LOGIC HIGH
Following the filter section is a decoder employing digital counting techniques to determine the frequencies of the
incoming tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm
protects against tone simulation by extraneous signals such as voice while providing tolerance to small frequency
deviations and variations. This averaging algorithm has been developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of interfering frequencies (third tones) and noise. When the
detector recognizes the presence of two valid tones (this is referred to as the “signal condition” in some industry
specifications) the “Early Steering” (ESt) output will go to an active state. Any subsequent loss of signal condition
will cause ESt to assume an inactive state.
4.0
Before registration of a decoded tone pair, the receiver checks for a valid signal duration (referred to as character
recognition condition). This check is performed by an external RC time constant driven by ESt. A logic high on ESt
causes v
remains high) for the validation period (t
tone pair, latching its corresponding 4-bit code (see Table 1) into the Receive Data Register. At this point the GT
output is activated and drives v
short delay to allow the output latch to settle, the delayed steering output flag goes high, signalling that a received
tone pair has been registered. The status of the delayed steering flag can be monitored by checking the appropriate
bit in the status register. If Interrupt mode has been selected, the IRQ/CP pin will pull low when the delayed steering
flag is active.
The contents of the output latch are updated on an active delayed steering transition. This data is presented to the
four bit bidirectional data bus when the Receive Data Register is read. The steering circuit works in reverse to
validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the
Steering Circuit
c
(see Figure 5) to rise as the capacitor discharges. Provided that the signal condition is maintained (ESt
F
697
697
697
770
770
770
852
852
852
941
941
941
697
770
852
941
LOW
c
to V
Table 1 - Functional Encode/Decode Table
F
DD
1209
1336
1477
1209
1336
1477
1209
1336
1477
1336
1209
1477
1633
1633
1633
1633
HIGH
. GT continues to drive high as long as ESt remains high. Finally, after a
GTP
), v
Zarlink Semiconductor Inc.
c
reaches the threshold (V
MT8888C
DIGIT
A
B
C
D
1
2
3
4
5
6
7
8
9
0
#
*
5
D
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
3
D
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
2
TSt
) of the steering logic to register the
D
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
D
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
Data Sheet