MT46H32M32LFB5-6 IT:B Micron Technology Inc, MT46H32M32LFB5-6 IT:B Datasheet
MT46H32M32LFB5-6 IT:B
Specifications of MT46H32M32LFB5-6 IT:B
Related parts for MT46H32M32LFB5-6 IT:B
MT46H32M32LFB5-6 IT:B Summary of contents
Page 1
... MHz -6 166 MHz -75 133 MHz PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/10 EN Products and specifications discussed herein are subject to change by Micron without notice. 1Gb: x16, x32 Mobile LPDDR SDRAM Options • DDQ – 1.8V/1.8V • Configuration – 64 Meg x 16 (16 Meg banks) – ...
Page 2
... FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. Micron’s FBGA part marking decoder is available at www.micron.com/decoder. PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM 64 Meg Meg banks 8 Meg banks 8K ...
Page 3
... Rev. D – 10/10 ........................................................................................................................................... 101 Rev. C – 10/10 ............................................................................................................................................ 101 Rev. B – 9/10 ............................................................................................................................................. 101 PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. Features © 2009 Micron Technology, Inc. All rights reserved. ...
Page 4
... Rev. A – 12/09 ............................................................................................................................................ 101 PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. Features © 2009 Micron Technology, Inc. All rights reserved. ...
Page 5
... Figure 47: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting ......................................................... 87 Figure 48: Bank Read – With Auto Precharge .................................................................................................. 90 Figure 49: Bank Read – Without Auto Precharge ............................................................................................. 91 Figure 50: Bank Write – With Auto Precharge .................................................................................................. 92 PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM t t DQSQ, QH, and Data Valid Window (x16) ................................................... 73 t ...
Page 6
... Figure 55: Power-Down Mode (Active or Precharge) ....................................................................................... 98 Figure 56: Deep Power-Down Mode .............................................................................................................. 99 Figure 57: Clock Stop Mode .......................................................................................................................... 100 PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. Features © 2009 Micron Technology, Inc. All rights reserved. ...
Page 7
... Table 20: Truth Table – Current State Bank n – Command to Bank m .............................................................. 49 Table 21: Truth Table – CKE .......................................................................................................................... 51 Table 22: Burst Definition Table .................................................................................................................... 57 PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. Features © 2009 Micron Technology, Inc. All rights reserved. ...
Page 8
... The 1Gb Mobile low-power DDR SDRAM is a high-speed CMOS, dynamic random-ac- cess memory containing 1,073,741,824 bits internally configured as a quad-bank DRAM. Each of the x16’s 268,435,456-bit banks is organized as 16,384 rows by 1024 col- umns by 16 bits. Each of the x32’s 268,435,456-bit banks is organized as 8192 rows by 1024 columns by 32 bits. In the reduced page-size (LG) option, each of the x32’ ...
Page 9
... Sense amplifiers I/O gating 2 DM mask logic Bank control logic 2 Column decoder Column- address counter/ latch 1 9 1Gb: x16, x32 Mobile LPDDR SDRAM Functional Block Diagrams Data Read MUX latch DRVRS 16 2 DQS generator COL 0 DQS Input CK 32 ...
Page 10
... Sense amplifiers I/O gating 2 DM mask logic Bank control logic 2 Column decoder Column- address counter/ latch 1 10 1Gb: x16, x32 Mobile LPDDR SDRAM Functional Block Diagrams Data Read MUX latch 32 2 DQS generator COL 0 DQS Input CK 64 registers ...
Page 11
... Ball Assignments and Descriptions Figure 4: 60-Ball VFBGA – Top View, x16 only Notes test pin that must be tied Unused address pins become RFU. PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM DQ15 V SS SSQ V DQ13 DQ14 DDQ V DQ11 ...
Page 12
... Figure 5: 90-Ball VFBGA – Top View, x32 only test pin that must be tied to V Notes: 2. Unused address pins become RFU. PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM DQ31 V SS SSQ V DQ29 DQ30 DDQ V DQ27 DQ28 SSQ V DQ25 ...
Page 13
... DQ4 DQ2 G DM0 PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/ DQ10 DQ12 DQ16 DQ19 CK SSQ DQ14 DQS1 DQ11 DQ8 DQ17 DQ18 RFU Top View – Ball Down 13 1Gb: x16, x32 Mobile LPDDR SDRAM Ball Assignments and Descriptions DQ20 DQS3 V DM2 V DQ21 DM3 SS DDQ ...
Page 14
... DQ21 DQ23 DQ9 DDQ DDQ DD V DQ20 DQ22 V CK# V DQ8 SSQ SSQ Top View – Ball Down 14 1Gb: x16, x32 Mobile LPDDR SDRAM Ball Assignments and Descriptions DQ11 V DQ13 DM1 V DQ15 DM3 DDQ DDQ DQ10 V DQ12 DQS1 V DQ14 DQS3 SSQ SSQ ...
Page 15
... It is used to capture data. Temperature sensor output: TQ HIGH when LPDDR T DQ power supply. DQ ground. Power supply. 15 1Gb: x16, x32 Mobile LPDDR SDRAM Ball Assignments and Descriptions in normal operations. exceeds 85°C. J Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 16
... Reserved for future use. Balls marked RFU may or may not be connected internally. These balls should not be used. Contact factory for details. 16 1Gb: x16, x32 Mobile LPDDR SDRAM Ball Assignments and Descriptions Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 17
... Solder ball material: SAC105 (98.5% Sn, 1% Ag, 0.5% Cu). Dimensions apply solder balls post-reflow on Ø0.4 SMD ball pads. 7.2 CTR 0.8 TYP 1. All dimensions are in millimeters. Note: PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM 0.65 ±0.05 Ball ±0 ...
Page 18
... Solder ball material: SAC105 (98.5% Sn, 1%Ag, 0.5% Cu). Dimensions apply to solder balls post reflow on Ø0.4 SMD ball pads. 11.2 CTR 0.8 TYP 1. All dimensions are in millimeters. Note: PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM 0.65 ±0.05 Ball ±0.1 ...
Page 19
... Solder ball material: SAC105 (98.5% Sn, 1% Ag, 0.5% Cu). Dimensions apply to solder balls post-reflow on Ø0.35 SMD ball pads ±0.1 CTR 0.65 TYP 1. All dimensions are in millimeters. Note: PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM 0.38 ±0.05 14 ±0.1 Ball ...
Page 20
... A 0.08 A 168X Ø0.34 Solder ball material: SAC105. Dimensions apply to solder balls post- reflow on Ø0. SMD ball pads. 11 CTR 0.5 TYP 1. All dimensions are in millimeters. Note: PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM 0.38 ±0.05 Ball ±0 ...
Page 21
... 0.7 × V IH(DC) V IL(DC) V 0.8 × V IH(AC) V IL(AC) = –0.1mA) V 0.9 × 0.1mA 1Gb: x16, x32 Mobile LPDDR SDRAM Electrical Specifications Min Max –1.0 2.4 –0.5 2 0.3V), DDQ whichever is less –55 150 DDQ Min Max Unit 1.70 1.95 1.70 1. 0.3 ...
Page 22
... CK and the input lev CK#. is expected to equal V IX variations in the DC level of the same added to DS and DH for each 100 mV/ns reduction in slew rate. If slew rate exceeds 4 V/ns, functionality is uncertain. 22 1Gb: x16, x32 Mobile LPDDR SDRAM Electrical Specifications Min Max – –40 85 –40 105 50 ...
Page 23
... IH(DC) V IL(DC) V 0.9 × V IH(AC) V IL(AC) = –0.1mA) V 0.9 × 0.1mA 1Gb: x16, x32 Mobile LPDDR SDRAM Electrical Specifications Min Max Unit 1.70 1.95 1.14 1. 0.2 DDQ DDQ –0.2 0.1 × V DDQ –0 0.2 DDQ V + 0.4 DDQ DDQ V + 0.4 DDQ DDQ 0.6 × V ...
Page 24
... MHz 25˚ OUT(DC) is grouped with I/O pins, reflecting the fact that they are matched in loading. for any given device. mum amount for any given device. 24 1Gb: x16, x32 Mobile LPDDR SDRAM Electrical Specifications Min Max Unit 1.5 3.0 pF – ...
Page 25
... Data bus inputs are stable Deep power-down current: Address and control balls are sta- ble; Data bus inputs are stable PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM Electrical Specifications – I Parameters 1.70–1.95V ...
Page 26
... Data bus inputs are stable Deep power-down current: Address and control pins are stable; Data bus inputs are stable PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM Electrical Specifications – 1.70–1.95V DD DDQ ...
Page 27
... Data bus inputs are stable Deep power-down current: Address and control balls are sta- ble; Data bus inputs are stable PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM Electrical Specifications – 1.70–1.95V DD DDQ ...
Page 28
... Data bus inputs are stable Deep power-down current: Address and control pins are stable; Data bus inputs are stable PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM Electrical Specifications – 1.70–1.95V DD DDQ ...
Page 29
... RFC later. t command period ( RFC (MIN)) else CKE is LOW (for example, during standby). 85˚C are guaranteed for the entire temperature range. All other I DD6 ues are estimated. 29 1Gb: x16, x32 Mobile LPDDR SDRAM /V = 1.70–1.95V DD DDQ Symbol Value I n/a ...
Page 30
... PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM Electrical Specifications – I -20 - Temperature ('C) 30 Micron Technology, Inc. reserves the right to change products or specifications without notice. Parameters © ...
Page 31
... Mobile LPDDR SDRAM = 1.14–1.30V) DDQ -6 -75 Min Max Min Max 2.0 5.0 2.0 6.0 2.0 6.5 2.0 6.5 – – ...
Page 32
... Mobile LPDDR SDRAM = 1.14–1.30V) DDQ -6 -75 Min Max Min Max DQSQ QH - DQSQ t t – – CH, CH – ...
Page 33
... For the half-strength driver with a nominal 10pF load, parameters are expected the same range. However, these parameters are not subject to production test but are estimated by design/characterization. Use of IBIS or other simula- 33 1Gb: x16, x32 Mobile LPDDR SDRAM = 1.14–1.30V) DDQ -6 -75 ...
Page 34
... V/ns. added, therefore, it remains constant. If the slew rate exceeds 4.5 V/ns, functionality is uncertain. fied prior to the internal PRECHARGE command being issued. 34 1Gb: x16, x32 Mobile LPDDR SDRAM 50 10pF or to the crossing point for CK/CK#. The output tim- . ...
Page 35
... If a previous WRITE was in progress, DQS could be HIGH t during this time, depending on DQSS. a greater value for this parameter, but system performance (bus turnaround) will de- grade accordingly. 35 1Gb: x16, x32 Mobile LPDDR SDRAM t WR time when in auto precharge mode ...
Page 36
... I-V curves. 36 1Gb: x16, x32 Mobile LPDDR SDRAM Output Drive Characteristics Pull-Up Current (mA) Min 0.00 –2.80 –5.60 –8.40 –11.20 –14.00 –16.80 –19.60 – ...
Page 37
... I-V curves. 37 1Gb: x16, x32 Mobile LPDDR SDRAM Output Drive Characteristics Pull-Up Current (mA) Min 0.00 –1.96 –3.92 –5.88 –7.84 –9.80 –11.76 –13.72 – ...
Page 38
... I-V curves. strength. 38 1Gb: x16, x32 Mobile LPDDR SDRAM Output Drive Characteristics Pull-Up Current (mA) Min 0.00 –1.27 –2.55 –3.82 –5.09 –6.36 –7.64 –8.91 – ...
Page 39
... Functional Description The Mobile LPDDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O. Single read or write access for the device consists of a single 2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit-wide, one-half-clock- cycle data transfers at the I/O ...
Page 40
... READ bursts with auto precharge enabled and for WRITE bursts. LOW. A10 HIGH: all banks are precharged and BA0–BA1 are “Don’t Care.” are “Don’t Care” except for CKE. 40 1Gb: x16, x32 Mobile LPDDR SDRAM RAS# CAS# WE# Address ...
Page 41
... A[0:n] selects the row. This row remains active for accesses until a PRE- CHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM Valid ...
Page 42
... PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/10 EN CK# CK CKE HIGH CS# WE# Row Bank Don’t Care 42 1Gb: x16, x32 Mobile LPDDR SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. Commands ...
Page 43
... CK# CK CKE HIGH CS# RAS# WE# Column EN AP A10 DIS AP Bank Don’t Care 43 1Gb: x16, x32 Mobile LPDDR SDRAM WTR are satisfied. Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. Commands ...
Page 44
... A10 DIS AP Bank Don’t Care t RP) after the PRECHARGE command is issued. Input A10 determines 44 1Gb: x16, x32 Mobile LPDDR SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. Commands ...
Page 45
... AUTO REFRESH AUTO REFRESH is used during normal operation of the device and is analogous to CAS#- BEFORE-RAS# (CBR) REFRESH in FPM/EDO DRAM. The AUTO REFRESH command is nonpersistent and must be issued each time a refresh is required. Addressing is generated by the internal refresh controller. This makes the address bits a “ ...
Page 46
... CAS# Address BA0, BA1 PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/10 EN CK# CK CKE CS# WE# Don’t Care 46 1Gb: x16, x32 Mobile LPDDR SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. Commands ...
Page 47
... RP is met, the bank will be in the idle state. Row activating: Starts with registration of an ACTIVE command and ends when t met. After RCD is met, the bank will be in the row active state. 47 1Gb: x16, x32 Mobile LPDDR SDRAM t is HIGH and after XSR has been met ( ...
Page 48
... READs or WRITEs with auto precharge disabled. BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE com- mand. 48 1Gb: x16, x32 Mobile LPDDR SDRAM has been met. After RP is met, the bank will has been met ...
Page 49
... For read with auto precharge, the precharge period is defined as if the same burst was 49 1Gb: x16, x32 Mobile LPDDR SDRAM t is HIGH and after XSR has been met (if ...
Page 50
... WRITE or WRITE with auto precharge PRECHARGE ACTIVE banks are idle. BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE com- mand. 50 1Gb: x16, x32 Mobile LPDDR SDRAM ends, with WR measured as if auto t RP) begins. This device supports concurrent auto ...
Page 51
... CKE Notes: 2. Current state is the state of the DDR SDRAM immediately prior to clock edge n. 3. COMMAND 4. All states and sequences not shown are illegal or reserved. 5. DESELECT or NOP commands should be issued on each clock edge occurring during the 6. After exiting deep power-down mode, a full DRAM initialization sequence is required. ...
Page 52
... WRITE A PRE ACT = ACTIVE AREF = AUTO REFRESH BST = BURST TERMINATE CKEH = Exit power-down CKEL = Enter power-down DPD = Enter deep power-down PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM Self refresh DPDX Deep SREFX power- down SREF DPD SRR ...
Page 53
... Typically, both of these commands are issued at this stage as de- scribed above. desired. the desired operating modes. Note that the sequence in which the standard and extended mode registers are programmed is not critical. 53 1Gb: x16, x32 Mobile LPDDR SDRAM ) must be brought up simultaneously. DDQ be from the same power source DDQ t ...
Page 54
... High High RFC FRESH command; ACT = ACTIVE command. 54 1Gb: x16, x32 Mobile LPDDR SDRAM Tb0 Tc0 Td0 ( ( ( ( ( ( ) ) ) ) ) ) ( ( ( ( ( ( ) ) ) ) ) ) ( ( ( ( ( ( ) ) ) ) ) ) ...
Page 55
... NOP PRE FRESH command; ACT = ACTIVE command. 55 1Gb: x16, x32 Mobile LPDDR SDRAM Tb0 Tc0 Td0 ( ( ( ( ( ( ) ) ) ) ) ) ( ( ( ( ( ( ) ) ) ) ) ) ( ( ( ( ( ( ) ) ) ) ) ...
Page 56
... M10 Operating Mode Normal operation – – – – – All other states reserved 1Gb: x16, x32 Mobile LPDDR SDRAM Standard Mode Register t MRD before initiating the subse Address bus Standard mode register (Mx) CAS Latency BT Burst Length Burst Length Reserved ...
Page 57
... 1Gb: x16, x32 Mobile LPDDR SDRAM Standard Mode Register Type = Interleaved 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 58
... A-B-C-D-E-F-0-1-2-3-4-5-6-7-8 B-C-D-E-F-0-1-2-3-4-5-6-7-8-9 C-D-E-F-0-1-2-3-4-5-6-7-8-9-A D-E-F-0-1-2-3-4-5-6-7-8-9-A-B E-F-0-1-2-3-4-5-6-7-8-9-A-B-C F-0-1-2-3-4-5-6-7-8-9-A-B-C-D-E t AC). For the READ command is regis- 58 1Gb: x16, x32 Mobile LPDDR SDRAM Standard Mode Register Type = Interleaved 0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F 1-0-3-2-5-4-7-6-9-8-B-A-D-C-F-E 2-3-0-1-6-7-4-5-A-B-8-9-E-F-C-D 3-2-1-0-7-6-5-4-B-A-9-8-F-E-D-C 4-5-6-7-0-1-2-3-C-D-E-F-8-9-A-B 5-4-7-6-1-0-3-2-D-C-F-E-9-8-B-A 6-7-4-5-2-3-0-1-E-F-C-D-A-B-8-9 7-6-5-4-3-2-1-0-F-E-D-C-B-A-9-8 8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7 9-8-B-A-D-C-F-E-1-0-3-2-5-4-7-6 A-B-8-9-E-F-C-D-2-3-0-1-6-7-4-5 B-A-9-8-F-E-D-C-3-2-1-0-7-6-5-4 C-D-E-F-8-9-A-B-4-5-6-7-0-1-2-3 D-C-F-E-9-8-B-A-5-4-7-6-1-0-3-2 E-F-C-D-A-B-8-9-6-7-4-5-2-3-0-1 F-E-D-C-B-A-9-8-7-6-5-4-3-2-1-0 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 59
... PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/ T1n CK# CK READ NOP DQS CK# CK READ NOP DQS DQ 59 1Gb: x16, x32 Mobile LPDDR SDRAM Standard Mode Register T2 T2n T3 T3n NOP NOP OUT OUT OUT OUT T2n T3 T3n NOP NOP t AC ...
Page 60
... Operation E7–E0 Normal AR operation Valid – All other states reserved 60 1Gb: x16, x32 Mobile LPDDR SDRAM Extended Mode Register Address bus Extended mode 1 TCSR PASR register (Ex Partial-Array Self Refresh Coverage Full array 1/2 array 1/4 array Reserved Reserved 1/8 array ...
Page 61
... The output driver settings are 25Ω, 37Ω, and 55Ω internal impedance for full, three-quarter, and one-half drive strengths, respectively. PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM Extended Mode Register 61 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 62
... T4 t SRR 2 LMR NOP READ 0 BA0 = 1 BA1 = SRR), and between the READ and the next VALID command ( as an example only. 62 1Gb: x16, x32 Mobile LPDDR SDRAM Status Read Register t SRC after the SRR READ com SRC NOP NOP NOP SRR out Don’ ...
Page 63
... IBIS (pull pull-down characteristics), or process occurs quired average periodic refresh interval = 63 1Gb: x16, x32 Mobile LPDDR SDRAM Status Read Register I/O bus (CLK L->H edge) DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 ...
Page 64
... The mini- mum time interval between successive ACTIVE commands to different banks is defined t by RRD. PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM t RCD specification. 64 Micron Technology, Inc. reserves the right to change products or specifications without notice. Bank/Row Activation t RC. © ...
Page 65
... READ command, where x equals the number of desired data element pairs. This is shown in Figure 32 (page 72). Following the PRECHARGE command, a subsequent PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM t DQSQ (valid data-out skew), t DQSCK (DQS transition skew to CK) and 65 Micron Technology, Inc ...
Page 66
... T1 T1n T2 T2n NOP NOP OUT OUT T1 T2 T2n NOP NOP data-out from column n. OUT t t AC, DQSCK, and 66 1Gb: x16, x32 Mobile LPDDR SDRAM READ Operation met. Part of the row precharge T3 T3n T4 NOP NOP OUT OUT T3 T3n T4 NOP NOP OUT OUT OUT OUT Don’ ...
Page 67
... NOP READ Bank, Col OUT OUT T2n NOP READ Bank, Col ( data-out from column n (or column b). OUT the first AC, DQSCK, and 67 1Gb: x16, x32 Mobile LPDDR SDRAM READ Operation T3 T3n T4 T4n T5 NOP NOP NOP OUT OUT OUT OUT OUT T3n T4 T4n ...
Page 68
... OUT T1n T2 T2n T3 NOP NOP READ Bank, Col OUT data-out from column n (or column b). OUT t t AC, DQSCK, and tive READs. 68 1Gb: x16, x32 Mobile LPDDR SDRAM READ Operation T3n T4 T4n T5 T5n NOP NOP OUT OUT T3n T4 T4n T5 T5n NOP NOP ...
Page 69
... READ Bank, Address Col n DQS Notes ( 16, the following burst interrupts the previous). 3. READs are to an active row in any bank. 4. Shown with nominal PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM T1 T1n T2 T2n READ READ Bank, Bank, Col x Col ...
Page 70
... DQ T0 CK# CK Command 1 READ Bank a, Address Col n DQS 16. Notes: 2. BST = BURST TERMINATE command; page remains open Shown with nominal 5. CKE = HIGH. PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM T1 T1n T2 T2n 2 BST NOP OUT OUT T2n 2 BST NOP ...
Page 71
... BST NOP OUT OUT T2n 2 BST NOP mand shown can be NOP data-out from column n. OUT b = data-in from column AC, DQSCK, and 71 1Gb: x16, x32 Mobile LPDDR SDRAM READ Operation T3 T3n T4 T4n T5 1 WRITE NOP NOP Bank, Col b t DQSS (NOM b+1 b+2 T3 ...
Page 72
... PRE Bank all data-out from column n. OUT t t AC, DQSCK, and cause a precharge to be performed at x number of clock cycles after the READ com- mand, where x = BL/2. 72 1Gb: x16, x32 Mobile LPDDR SDRAM READ Operation T3 T3n T4 T5 NOP NOP ACT Bank a, Row t RP ...
Page 73
... DQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transition and ends with the last valid DQ transition. er byte and UDQS defines the upper byte derived from HP 1Gb: x16, x32 Mobile LPDDR SDRAM READ Operation T3 T3n ...
Page 74
... DQSQ is derived at each DQS clock edge and is not cumulative over time; it begins with DQS transition and ends with the last valid DQ transition derived from HP byte 2; DQ[31:23] and DQS3 for byte 3. 74 1Gb: x16, x32 Mobile LPDDR SDRAM READ Operation T3 T3n 2,3 ...
Page 75
... NOP NOP DQSCK RPRE T2n DQSQ after DQS transitions, regardless the DQ output window relative to CK and is the long-term component of DQ skew. 75 1Gb: x16, x32 Mobile LPDDR SDRAM READ Operation T3n T4 T4n T5 T5n 1 1 NOP NOP t DQSCK T4 T3 T3n T4n DQSQ window. ...
Page 76
... Data for any WRITE burst can be followed by a subsequent PRECHARGE command. To follow a WRITE without truncating the WRITE burst, Figure 45 (page 85). PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM DQSS [MAX]) might not be obvious, they have also been included. Figure 38 76 Micron Technology, Inc ...
Page 77
... DSH (MIN) generally occurs during t DSS (MIN) generally occurs during trols DQ[7:0], DQS1 controls DQ[15:8], DQS2 controls DQ[23:16], and DQS3 controls DQ[31:24]. trols DQ[7:0], DM1 controls DQ[15:8], DM2 controls DQ[23:16], and DM3 controls DQ[31:24]. 77 1Gb: x16, x32 Mobile LPDDR SDRAM WRITE Operation met. T2 T2n T3 3 ...
Page 78
... IS IH Note 4 Bank DQSS (NOM) RCD t RAS t t WPRE WPRES these times data-in from column 1Gb: x16, x32 Mobile LPDDR SDRAM WRITE Operation T4n T5 T5n NOP NOP NOP DQSL DQSH WPST Don’t Care Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 79
... DQSS DQS b DQSS DQS b DQSS DQS Don’t Care b = data-in for column 1Gb: x16, x32 Mobile LPDDR SDRAM WRITE Operation T2 T2n T3 NOP NOP b+2 b b+2 b b+1 b+2 b+3 Transitioning Data Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 80
... CK# CK Command 1, 2 WRITE Bank, Address Col b t DQSS (NOM) DQS Each WRITE command can be to any bank. Notes uninterrupted burst shown PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM T1 T1n T2 T2n 1, 2 NOP WRITE Bank, Col b+1 ...
Page 81
... Rev. E 12/ T1n T2 T2n 1,2 1,2 WRITE WRITE Bank, Bank, Col x Col b’ x x’ data-in for column b ( g). IN med burst order. 81 1Gb: x16, x32 Mobile LPDDR SDRAM WRITE Operation T3 T3n T4 T4n T5 1,2 1,2 WRITE WRITE NOP Bank, Bank, Col a Col n’ a a’ ...
Page 82
... READ command could be applied earlier. t WTR is referenced from the first positive CK edge after the last data-in pair data-in for column data-out for column n. IN OUT 82 1Gb: x16, x32 Mobile LPDDR SDRAM WRITE Operation T5n T4 T5 READ NOP 4 Bank a, ...
Page 83
... b+1 t WTR is referenced from the first positive CK edge after the last data-in pair data-in for column data-out for column n. IN OUT 83 1Gb: x16, x32 Mobile LPDDR SDRAM WRITE Operation T4 T5 T5n NOP NOP Don’t Care Transitioning Data Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 84
... WTR is referenced from the first positive CK edge after the last data-in pair data-in for column data-out for column n. IN OUT 84 1Gb: x16, x32 Mobile LPDDR SDRAM WRITE Operation T4 T5 T5n NOP NOP Don’t Care Transitioning Data Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 85
... CHARGE and WRITE commands can be to different devices; in this case, required and the PRECHARGE command can be applied earlier referenced from the first positive CK edge after the last data-in pair data-in for column 1Gb: x16, x32 Mobile LPDDR SDRAM WRITE Operation T4 T5 3,4 NOP PRE ...
Page 86
... referenced from the first positive CK edge after the last data-in pair data-in for column 1Gb: x16, x32 Mobile LPDDR SDRAM WRITE Operation T3n T4 T4n T5 3 PRE NOP Bank (a or all) Don’t Care Transitioning Data Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 87
... T2n T3 NOP NOP NOP referenced from the first positive CK edge after the last data-in pair data-in for column 1Gb: x16, x32 Mobile LPDDR SDRAM WRITE Operation T3n T4 T4n T5 3 NOP PRE Bank (a or all) Don’t Care Transitioning Data Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 88
... Figure 49 (page 91). Bank WRITE operations with and without auto precharge are shown in Figure 50 (page 92) and Figure 51 (page 93). PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM t RP) after the PRECHARGE command is issued. Input A10 deter (the precharge period) begins. For READ with auto pre- ...
Page 89
... PRECHARGE command, thus freeing the command bus for operations in other banks. PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM 89 Micron Technology, Inc. reserves the right to change products or specifications without notice. Auto Precharge © 2009 Micron Technology, Inc. All rights reserved. ...
Page 90
... NOP READ NOP Col n Note Bank x t RCD t RAS RPRE t AC (MIN (MIN (MIN) these times data-out from column n. OUT 90 1Gb: x16, x32 Mobile LPDDR SDRAM Auto Precharge T5 T5n T6 T6n NOP NOP DQSCK (MIN) t RPST OUT OUT OUT OUT RPRE DQSCK (MAX) ...
Page 91
... RCD 6 t RAS RPRE t AC (MIN (MIN) D OUT (MIN) t RPRE t AC (MAX) these times data out from column n. OUT 91 1Gb: x16, x32 Mobile LPDDR SDRAM Auto Precharge T5 T5n T6 T6n PRE NOP NOP All banks One bank 5 Bank DQSCK (MIN) t RPST OUT ...
Page 92
... IH IS Bank DQSS (NOM) RCD t RAS t t WPRE WPRES these times data-out from column 1Gb: x16, x32 Mobile LPDDR SDRAM Auto Precharge T4n T5 T5n NOP NOP NOP DQSL DQSH WPST t DH Don’t Care Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 93
... RCD t RAS t DQSS (NOM WPRES WPRE these times data-out from column n. OUT 93 1Gb: x16, x32 Mobile LPDDR SDRAM Auto Precharge T4n T5 T5n NOP NOP NOP DQSL DQSH WPST Don’t Care Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 94
... AUTO REFRESH Operation Auto refresh mode is used during normal operation of the device and is analogous to CAS#-BEFORE-RAS# (CBR) REFRESH in FPM/EDO DRAM. The AUTO REFRESH com- mand is nonpersistent and must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits a “ ...
Page 95
... SELF REFRESH command must not be used as a substitute for the AUTO REFRESH command. PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM t XSR to complete any internal refresh already in progress. 95 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 96
... Care.” The power-down state is synchronously exited when CKE is registered HIGH (in conjunction with a NOP or DESELECT command). NOP or DESELECT commands must be maintained on the command bus until satisfied. See Figure 55 (page 98) for a detailed illustration of power-down mode. PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM T1 Ta0 ( ( ) ...
Page 97
... Figure 54: Power-Down Entry (in Active or Precharge Mode) RAS#, CAS#, WE# RAS#, CAS#, WE# PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM CK# CK CKE CS# Or CS# Address BA0, BA1 Don’t Care 97 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 98
... LOW to maintain DPD mode. The clock must be stable prior to exiting DPD mode. To exit DPD mode, assert CKE HIGH with either a NOP or DESELECT com- mand present on the command bus. After exiting DPD mode, a full DRAM initialization sequence is required. PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m ...
Page 99
... All banks idle with no activity on the data bus 1. Clock must be stable prior to CKE going HIGH. Notes: 2. DPD = deep power-down. 3. Upon exit of deep power-down mode, a full DRAM initialization sequence is required. PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM 1 T1 ...
Page 100
... The device enables the clock to change frequency during operation only if all timing parameters are met and all refresh requirements are satisfied. The clock can be stopped altogether if there are no DRAM operations in progress that would be affected by this change. Any DRAM operation already in process must be com- pleted before entering clock stop mode ...
Page 101
... This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization some- PDF: 09005aef83d9bee4 1gb_ddr_mobile_sdram_t68m.pdf - Rev. E 12/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM t t DQSK and AC values from 5 ...