MT48LC2M32B2P-7:G TR Micron Technology Inc, MT48LC2M32B2P-7:G TR Datasheet - Page 50

DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II T/R

MT48LC2M32B2P-7:G TR

Manufacturer Part Number
MT48LC2M32B2P-7:G TR
Description
DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II T/R
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet

Specifications of MT48LC2M32B2P-7:G TR

Density
64 Mb
Maximum Clock Rate
143 MHz
Package
86TSOP-II
Address Bus Width
13 Bit
Operating Supply Voltage
3.3 V
Maximum Random Access Time
17|8|5.5 ns
Operating Temperature
0 to 70 °C
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
64M (2Mx32)
Speed
143MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Package / Case
86-TSOP
Organization
2Mx32
Address Bus
13b
Access Time (max)
17/8/5.5ns
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
160mA
Pin Count
86
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1073-2
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
23. The clock frequency must remain constant during access or precharge states (READ,
24. Auto precharge mode only.
25. JEDEC and PC100 specify three clocks.
26.
27. V
28. Check factory for availability of specially screened devices having
WRITE, including
data rate.
t
t
CK = 7ns for -7, 6ns for -6, 5.5ns for -55, and 5ns for -5.
CK for 100 MHz and slower (
DD
(MIN) = 3.135V for -6, -55, and -5 speed grades.
t
WR, and PRECHARGE commands). CKE may be used to reduce the
50
t
CK = 10ns and higher) in manual precharge.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
64Mb: x32 SDRAM
t
WR = 10ns.
t
Notes
WR = 1

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