MT48LC4M32B2B5-7:G Micron Technology Inc, MT48LC4M32B2B5-7:G Datasheet - Page 53

DRAM Chip SDRAM 128M-Bit 4Mx32 3.3V 90-Pin VFBGA Tray

MT48LC4M32B2B5-7:G

Manufacturer Part Number
MT48LC4M32B2B5-7:G
Description
DRAM Chip SDRAM 128M-Bit 4Mx32 3.3V 90-Pin VFBGA Tray
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet

Specifications of MT48LC4M32B2B5-7:G

Density
128 Mb
Maximum Clock Rate
143 MHz
Package
90VFBGA
Address Bus Width
14 Bit
Operating Supply Voltage
3.3 V
Maximum Random Access Time
17|8|5.5 ns
Operating Temperature
0 to 70 °C
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
128M (4Mx32)
Speed
143MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Package / Case
90-VFBGA
Organization
4Mx32
Address Bus
14b
Access Time (max)
17/8/5.5ns
Operating Supply Voltage (typ)
3.3V
Package Type
VFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
175mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT48LC4M32B2B5-7:G
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
MT48LC4M32B2B5-7:G TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Figure 36:
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. L 1/09 EN
A0–A9, A11
Auto Refresh Mode
COMMAND
BA0, BA1
DQM 0-3
Notes:
A10
CKE
CLK
DQ
Precharge all
High-Z
t CKS
active banks
t CMS
t AS
SINGLE BANK
PRECHARGE
ALL BANKS
BANK(S)
T0
1.
t AH
t CKH
t CMH
t CK
t
commands must be applied on each positive clock edge during
RFC must not be interrupted by any executable command; COMMAND INHIBIT or NOP
t RP
T1
NOP
T2
REFRESH
AUTO
t CH
t RFC
53
NOP
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
t CL
Tn + 1
REFRESH
AUTO
t RFC
NOP
DON’T CARE
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©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM
RFC.
To + 1
ACTIVE
ROW
ROW
BANK
Timing Diagrams
UNDEFINED

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