72T18125L5BBI Integrated Device Technology (Idt), 72T18125L5BBI Datasheet - Page 27

• Manufacturer Part Number: 72T18125L5BBI
• Description: FIFO Mem Async/Sync Dual Depth/Width Uni-Dir 512K x 18/1M x 9 240-Pin BGA
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72T18125L5BBI

• Package: 240BGA
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 9 Mb
• Organization: 512Kx18|1Mx9
• Data Bus Width: 9/18 Bit
• Timing Type: Asynchronous|Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 2.5 V
• Operating Temperature: -40 to 85 °C

on the LOW-to-HIGH transition of the Read Clock (RCLK). PAE is reset to HIGH
on the LOW-to-HIGH transition of the Write Clock (WCLK). If synchronous PAE
configuration is selected, the PAE is updated on the rising edge of RCLK. See
Figure 26, Asynchronous Programmable Almost-Empty Flag Timing (IDT
Standard and FWFT Mode), for the relevant timing information.
HALF-FULL FLAG (HF)
beyond half-full sets HF LOW. The flag remains LOW until the difference
between the write and read pointers becomes less than or equal to half of the
total depth of the device; the rising RCLK edge that accomplishes this condition
sets HF HIGH.
HF will go LOW after (D/2 + 1) writes to the FIFO. If x18 Input or x18 Output
bus Width is selected, D = 2,048 for the IDT72T1845, 4,096 for the IDT72T1855,
8,192 for the IDT72T1865, 16,384 for the IDT72T1875, 32,768 for the
IDT72T1885, 65,536 for the IDT72T1895, 131,072 for the IDT72T18105,
262,144 for the IDT72T18115 and 524,288 for the IDT72T18125. If both x9
Input and x9 Output bus Widths are selected, D = 4,096 for the IDT72T1845,
8,192 for the IDT72T1855, 16,384 for the IDT72T1865, 32,768 for the
IDT72T1875, 65,536 for the IDT72T1885, 131,072 for the IDT72T1895,
262,144 for the IDT72T18105, 524,288 for the IDT72T18115 and 1,048,576
for the IDT72T18125.
will go LOW after (D-1/2 + 2) writes to the FIFO. If x18 Input or x18 Output bus
Width is selected, D = 2,049 for the IDT72T1845, 4,097 for the IDT72T1855,
8,193 for the IDT72T1865, 16,385 for the IDT72T1875, 32,769 for the
IDT72T1885, 65,537 for the IDT72T1895, 131,073 for the IDT72T18105,
262,145 for the IDT72T18115 and 524,289 for the IDT72T18125. If both x9
Input and x9 Output bus Widths are selected, D = 4,097 for the IDT72T1845,
8,193 for the IDT72T1855, 16,385 for the IDT72T1865, 32,769 for the
IDT72T1875, 65,537 for the IDT72T1885, 131,073 for the IDT72T1895,
262,145 for the IDT72T18105, 524,289 for the IDT72T18115 and 1,048,577
for the IDT72T18125.
for the relevant timing information. Because HF is updated by both RCLK and
WCLK, it is considered asynchronous.
Q
NOTES:
1. REN is LOW;RCS is LOW.
2. t
3. Qslowest is the data output with the slowest access time, t
4. Time, t
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
SLOWEST
ERCLK
ERCLK
If asynchronous PAE configuration is selected, the PAE is asserted LOW
This output indicates a half-full FIFO. The rising WCLK edge that fills the FIFO
In IDT Standard mode, if no reads are performed after reset (MRS or PRS),
In FWFT mode, if no reads are performed after reset (MRS or PRS), HF
See Figure 27, Half-Full Flag Timing (IDT Standard and FWFT Mode),
RCLK
Figure 4. Echo Read Clock and Data Output Relationship
(3)
> t
D
is greater than zero, guaranteed by design.
A
, guaranteed by design.
t
A
t
ERCLK
t
D
t
ERCLK
A
.
5909 drw08
27
ECHO READ CLOCK (ERCLK)
selectable via RHSTL. The ERCLK is a free-running clock output, it will always
follow the RCLK input regardless of REN, RCS.
delay provides the user with a more effective read clock source when reading
data from the Qn outputs. This is especially helpful at high speeds when
variables within the device may cause changes in the data access times. These
variations in access time maybe caused by ambient temperature, supply
voltage, device characteristics. The ERCLK output also compensates for any
trace length delays between the Qn data outputs and receiving devices inputs.
effect on the ERCLK output produced by the FIFO device, therefore the ERCLK
output level transitions should always be at the same position in time relative to
the data outputs. Note, that ERCLK is guaranteed by design to be slower than
the slowest Qn, data output. Refer to Figure 4, Echo Read Clock and Data
Output Relationship, Figure 28, Echo Read Clock & Read Enable Operation
and Figure 29, Echo RCLK & Echo REN Operation for timing information.
ECHO READ ENABLE (EREN)
selectable via RHSTL.
output and provides the reading device with a more effective scheme for reading
data from the Qn output port at high speeds. The EREN output is controlled by
internal logic that behaves as follows: The EREN output is active LOW for the
RCLK cycle that a new word is read out of the FIFO. That is, a rising edge of
RCLK will cause EREN to go active, LOW if both REN and RCS are active, LOW
and the FIFO is NOT empty.
SERIAL CLOCK (SCLK)
on the SCLK input is used to load serial data present on the SI input provided
that the SEN input is LOW.
DATA OUTPUTS (Q
9-bit wide data.
The Echo Read Clock output is provided in both HSTL and LVTTL mode,
The ERCLK output follows the RCLK input with an associated delay. This
Any variations effecting the data access time will also have a corresponding
The Echo Read Enable output is provided in both HSTL and LVTTL mode,
The EREN output is provided to be used in conjunction with the ERCLK
During serial loading of the programming flag offset registers, a rising edge
(Q
0
- Q
17
2Kx18/4Kx9, 4Kx18/
) data outputs for 18-bit wide data or (Q
0
-Q
n
)
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 10, 2009
0
- Q
8
) data outputs for