72T18125L5BBI Integrated Device Technology (Idt), 72T18125L5BBI Datasheet - Page 53

• Manufacturer Part Number: 72T18125L5BBI
• Description: FIFO Mem Async/Sync Dual Depth/Width Uni-Dir 512K x 18/1M x 9 240-Pin BGA
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72T18125L5BBI

• Package: 240BGA
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 9 Mb
• Organization: 512Kx18|1Mx9
• Data Bus Width: 9/18 Bit
• Timing Type: Asynchronous|Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 2.5 V
• Operating Temperature: -40 to 85 °C

OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
signals of multiple devices. Status flags can be detected from any one device.
The exceptions are the EF and FF functions in IDT Standard mode and the IR
and OR functions in FWFT mode. Because of variations in skew between RCLK
and WCLK, it is possible for EF/FF deassertion and IR/OR assertion to vary
by one cycle between FIFOs. In IDT Standard mode, such problems can be
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
Word width may be increased simply by connecting together the control
GATE
For the x18 Input or x18 Output bus Width: 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 18, 32,768 x 18, 65,536 x 36, 131,072 x 36,
For both x9 Input and x9 Output bus Widths: 4,096 x 18, 8,192 x 18, 16,384 x 18, 32,768 x 18, 65,536 x 18, 131,072 x 18, 262,144 x 18,
(1)
FIRST WORD FALL THROUGH/
DATA IN
SERIAL INPUT (FWFT/SI)
SERIAL CLOCK (SCLK)
PARTIAL RESET (PRS)
MASTER RESET (MRS)
FULL FLAG/INPUT READY (FF/IR)
FULL FLAG/INPUT READY (FF/IR) #2
RETRANSMIT (RT)
m + n
PROGRAMMABLE (PAF)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
HALF-FULL FLAG (HF)
D
0
- D
LOAD (LD)
m
m
#1
Figure 36. Block Diagram of Width Expansion
72T18105
72T18115
72T18125
72T1845
72T1855
72T1865
72T1875
72T1885
72T1895
FIFO
524,288 x 18 and 1,048,576 x 18
IDT
#1
262,144 x 36 and 524,288 x 36
D
m+1
m
- D
Q
53
n
0
n
- Qm
avoided by creating composite flags, that is, ANDing EF of every FIFO, and
separately ANDing FF of every FIFO. In FWFT mode, composite flags can be
created by ORing OR of every FIFO, and separately ORing IR of every FIFO.
72T1855/72T1865/72T1875/72T1885/72T1895/72T18105/72T18115/
72T18125 devices. D
Q
be attained by adding additional IDT72T1845/72T1855/72T1865/72T1875/
72T1885/72T1895/72T18105/72T18115/72T18125 devices.
0
-Q
Figure 36 demonstrates a width expansion using two IDT72T1845/
72T18105
72T18115
72T18125
72T1845
72T1855
72T1865
72T1875
72T1885
72T1895
17
FIFO
IDT
#2
from each device form a 36-bit wide output bus. Any word width can
2Kx18/4Kx9, 4Kx18/
READ CLOCK (RCLK)
READ CHIP SELECT (RCS)
n
READ ENABLE (REN)
OUTPUT ENABLE (OE)
EMPTY FLAG/OUTPUT READY (EF/OR) #2
EMPTY FLAG/OUTPUT READY (EF/OR) #1
PROGRAMMABLE (PAE)
Q
0
- D
m+1
17
- Q
from each device form a 36-bit wide input bus and
n
COMMERCIAL AND INDUSTRIAL
m + n
TEMPERATURE RANGES
DATA OUT
FEBRUARY 10, 2009
5909 drw40
GATE
(1)