XC3S500E-4FTG256C Xilinx Inc, XC3S500E-4FTG256C Datasheet - Page 130

• Manufacturer Part Number: XC3S500E-4FTG256C
• Description: FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 256-Pin FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S500E-4FTG256C

• Package: 256FTBGA
• Family Name: Spartan®-3E
• Device Logic Cells: 10476
• Device Logic Units: 1164
• Device System Gates: 500000
• Number Of Registers: 9312
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 190
• Ram Bits: 368640
• Number Of Logic Elements/cells: 10476
• Number Of Labs/clbs: 1164
• Total Ram Bits: 368640
• Number Of I /o: 190
• Number Of Gates: 500000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1536 - KIT STARTER SPARTAN-3E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1485

DC and Switching Characteristics
Table 90: Propagation Times for the IOB Input Path
Table 91: Input Timing Adjustments by IOSTANDARD
130
Notes:
1.
2.
Single-Ended Standards
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33_3
PCI66_3
HSTL_I_18
HSTL_III_18
SSTL18_I
SSTL2_I
Propagation Times
Following Signal Standard
Convert Input Time from
Symbol
T
T
IOPLID
The numbers in this table are tested using the methodology presented in
Table 77
This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When this is
true, add the appropriate Input adjustment from
IOPLI
LVCMOS25 to the
(IOSTANDARD)
and
The time it takes for data to
travel from the Input pin
through the IFF latch to the
I output with no input delay
programmed
The time it takes for data to
travel from the Input pin
through the IFF latch to the
I output with the input delay
programmed
Table
80.
Description
Adjustment Below
0.42
0.42
0.96
0.62
0.26
0.41
0.41
0.12
0.17
0.30
0.15
-5
Speed Grade
0
Add the
0.12
0.43
0.43
0.98
0.63
0.27
0.42
0.42
0.17
0.30
0.15
LVCMOS25
IFD_DELAY_VALUE = 0
LVCMOS25
IFD_DELAY_VALUE =
default software setting
-4
0
Table
Conditions
91.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
www.xilinx.com
(2)
(2)
,
,
Table 91: Input Timing Adjustments by IOSTANDARD
Notes:
1.
2.
Differential Standards
LVDS_25
BLVDS_25
MINI_LVDS_25
LVPECL_25
RSDS_25
DIFF_HSTL_I_18
DIFF_HSTL_III_18
DIFF_SSTL18_I
DIFF_SSTL2_I
Following Signal Standard
Convert Input Time from
Table 95
The numbers in this table are tested using the methodology
presented in
set forth in
These adjustments are used to convert input path times originally
specified for the LVCMOS25 standard to times that correspond to
other signal standards.
LVCMOS25 to the
DELAY_
VALUE=
(IOSTANDARD)
IFD_
0
2
3
and are based on the operating conditions set forth in
Table
XC3S100E
Table 95
All Others
Device
77,
All
Table
and are based on the operating conditions
80, and
Adjustment Below
DS312-3 (v3.8) August 26, 2009
Max
1.96
5.40
6.30
0.48
0.39
0.48
0.27
0.48
0.48
0.48
0.30
0.32
Speed Grade
-5
-5
Speed Grade
Table
Add the
Product Specification
82.
Max
2.25
5.97
7.20
0.49
0.39
0.49
0.27
0.49
0.49
0.49
0.30
0.32
-4
-4
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R