XC3S500E-4FTG256C Xilinx Inc, XC3S500E-4FTG256C Datasheet - Page 201

• Manufacturer Part Number: XC3S500E-4FTG256C
• Description: FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 256-Pin FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S500E-4FTG256C

• Package: 256FTBGA
• Family Name: Spartan®-3E
• Device Logic Cells: 10476
• Device Logic Units: 1164
• Device System Gates: 500000
• Number Of Registers: 9312
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 190
• Ram Bits: 368640
• Number Of Logic Elements/cells: 10476
• Number Of Labs/clbs: 1164
• Total Ram Bits: 368640
• Number Of I /o: 190
• Number Of Gates: 500000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1536 - KIT STARTER SPARTAN-3E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1485

Footprint Migration Differences
Table 147
ences between the XC3S250E, the XC3S500E, and the
XC3S1200E FPGAs that may affect easy migration
between devices in the FG256 package. There are 26 such
balls. All other pins not listed in
migrate between Spartan-3E devices available in the FT256
package.
The XC3S250E is duplicated on both the left and right sides
of the table to show migrations to and from the XC3S500E
Table 147: FT256 Footprint Migration Differences
DS312-4 (v3.8) August 26, 2009
Product Specification
FT256
Ball
D16
M14
N14
N15
R10
B10
E13
E16
P10
T12
L12
L13
M4
M7
B6
B7
C7
N2
N7
P7
F3
F4
F5
L2
L3
L4
Legend:
DIFFERENCES
This pin is identical on the device on the left and the right.
This pin can unconditionally migrate from the device on the left to the device on the right. Migration in the other direction may be possible
depending on how the pin is configured for the device on the right.
This pin can unconditionally migrate from the device on the right to the device on the left. Migration in the other direction may be possible
depending on how the pin is configured for the device on the left.
summarizes any footprint and functionality differ-
Bank
R
0
0
0
0
1
1
1
3
3
3
3
3
3
1
1
3
2
1
3
2
1
1
2
2
2
2
INPUT
N.C.
INPUT
N.C.
VREF(I/O)
N.C.
N.C.
N.C.
N.C.
I/O
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
INPUT
I/O
VREF(I/O)
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
INPUT
XC3S250E
Type
Table 147
Migration
19
unconditionally
INPUT
I/O
INPUT
I/O
VREF(INPUT)
I/O
I/O
I/O
VREF
I/O
VREF
I/O
I/O
I/O
I/O
I/O
INPUT
I/O
VREF(I/O)
I/O
I/O
VREF
I/O
I/O
VREF
INPUT
XC3S500E
Type
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and the XC3S1200E. The arrows indicate the direction for
easy migration. A double-ended arrow (
the two pins have identical functionality. A left-facing arrow
( ) indicates that the pin on the device on the right uncon-
ditionally migrates to the pin on the device on the left. It may
be possible to migrate the opposite direction depending on
the I/O configuration. For example, an I/O pin (Type = I/O)
can migrate to an input-only pin (Type = INPUT) if the I/O
pin is configured as an input.
Migration
7
I/O
I/O
I/O
I/O
VREF(INPUT)
I/O
I/O
I/O
VREF
INPUT
VREF
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
VREF(INPUT)
I/O
I/O
VREF
I/O
I/O
VREF
I/O
XC3S1200E
Type
Migration
Pinout Descriptions
26
) indicates that
INPUT
N.C.
INPUT
N.C.
VREF(I/O)
N.C.
N.C.
N.C.
N.C.
I/O
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
INPUT
I/O
VREF(I/O)
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
INPUT
XC3S250E
Type
201