XC3S500E-4FTG256C Xilinx Inc, XC3S500E-4FTG256C Datasheet - Page 33

• Manufacturer Part Number: XC3S500E-4FTG256C
• Description: FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 256-Pin FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S500E-4FTG256C

• Package: 256FTBGA
• Family Name: Spartan®-3E
• Device Logic Cells: 10476
• Device Logic Units: 1164
• Device System Gates: 500000
• Number Of Registers: 9312
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 190
• Ram Bits: 368640
• Number Of Logic Elements/cells: 10476
• Number Of Labs/clbs: 1164
• Total Ram Bits: 368640
• Number Of I /o: 190
• Number Of Gates: 500000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1536 - KIT STARTER SPARTAN-3E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1485

Table 18: Dual-Port RAM Function
DS312-2 (v3.8) August 26, 2009
Product Specification
Notes:
1.
2.
WE (mode)
1 (write)
0 (read)
1 (read)
1 (read)
1 (read)
data_a = word addressed by bits A3-A0.
data_d = word addressed by bits DPRA3-DPRA0.
Figure 27: Dual-Port RAM Component
R
Inputs
WCLK
DPRA0
DPRA1
DPRA2
DPRA3
WCLK
↑
X
0
1
↓
WE
A0
A1
A2
A3
D
DPRA[3:0]
RAM16X1D
WCLK
A[3:0]
D
X
X
X
D
X
WE
D
DS312-2_42_021305
SPO
DPO
data_a
data_a
data_a
data_a
SPO
D
Figure 26: RAM16X1D Dual-Port Usage
Outputs
data_d
data_d
data_d
data_d
data_d
DPO
www.xilinx.com
(Read/
Write)
RAM
(Read
16x1
RAM
16x1
Only)
LUT
LUT
Table 19: Distributed RAM Signals
WCLK
WE
A0, A1, A2,
A3 (A4, A5)
D
O, SPO, and
DPO
SLICEM
Signal
Optional
Register
Optional
Register
The clock is used for synchronous writes.
The data and the address input pins have
setup times referenced to the WCLK pin.
Active on the positive edge by default
with built-in programmable polarity.
The enable pin affects the write
functionality of the port. An inactive Write
Enable prevents any writing to memory
cells. An active Write Enable causes the
clock edge to write the data input signal
to the memory location pointed to by the
address inputs. Active High by default
with built-in programmable polarity.
The address inputs select the memory
cells for read or write. The width of the
port determines the required address
inputs.
The data input provides the new data
value to be written into the RAM.
The data output O on single-port RAM or
the SPO and DPO outputs on dual-port
RAM reflects the contents of the memory
cells referenced by the address inputs.
Following an active write clock edge, the
data out (O or SPO) reflects the newly
written data.
DS312-2_41_021305
SPO
DPO
Description
Functional Description
33