HS1-82C54RH-8 Intersil, HS1-82C54RH-8 Datasheet - Page 11

• Manufacturer Part Number: HS1-82C54RH-8
• Manufacturer: Intersil

Specifications of HS1-82C54RH-8

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Mode Definitions
The following are defined for use in describing the operation
of the HS-82C54RH.
CLK PULSE:
A rising edge, then a falling edge, in that order, of a
Counter’s CLK input.
TRIGGER:
A rising edge of a Counter’s Gate input.
COUNTER LOADING:
The transfer of a count from the CR to the CE (See
“Functional Description”)
Mode 0: Interrupt on Terminal Count
Mode 0 is typically used for event counting. After the Control
Word is written, OUT is initially low, and will remain low until
the Counter reaches zero. OUT then goes high and remains
high until a new count or a new Mode 0 Control Word is
written to the Counter.
GATE = 1 enables counting; GATE = 0 disables counting.
GATE has no effect on OUT.
After the Control Word and initial count are written to a
Counter, the initial count will be loaded on the next CLK
pulse. This CLK pulse does not decrement the count, so for
an initial count of N, OUT does not go high until N + 1 CLK
pulses after the initial count is written.
If a new count is written to the Counter it will be loaded on
the next CLK pulse and counting will continue from the new
count. If a two-byte count is written, the following happens:
1. Writing the first byte disables counting. OUT is set low
2. Writing the second byte allows the new count to be loaded
CS
0
0
0
0
0
0
0
0
1
0
immediately (no clock pulse required).
on next CLK pulse.
FIGURE 16. READ/WRITE OPERATIONS SUMMARY
RD
1
1
1
1
0
0
0
0
X
1
WR
X
0
0
0
0
1
1
1
1
1
A1
0
0
1
1
0
0
1
1
X
X
A0
X
X
0
1
0
1
0
1
0
1
11
Write into Counter 0
Write into Counter 1
Write into Counter 2
Write Control Word
Read from Counter 0
Read from Counter 1
Read from Counter 2
No-Operation (Three-State)
No-Operation (Three-State)
No-Operation (Three-State)
HS-82C54RH
This allows the counting sequence to be synchronized by
software. Again OUT does not go high until N + 1 CLK
pulses after the new count of N is written.
If an initial count is written while GATE = 0, it will still
beloaded on the next CLK pulse. When GATE goes high,
OUT will go high N CLK pulses later; no CLK pulse is
needed to load the Counter as this has already been done.
NOTES:
19. Counters are programmed for binary (not BCD) counting and for
20. The Counter is always selected (CS always low).
21. CW stands for “Control Word”; CW = 10 means a Control Word
22. LSB stands for “Least significant byte” of count.
23. Numbers below diagrams are count values. The lower number is
24. N stands for an undefined count.
25. Vertical lines show transitions between count values.
Mode 1: Hardware Retriggerable One-Shot
OUT will be initially high. OUT will go low on the CLK pulse
following a trigger to begin the one-shot pulse, and will
remain low until the Counter reaches zero. OUT will then go
high and remain high until the CLK pulse after the next
trigger.
After writing the Control Word and initial count, the Counter
is armed. A trigger results in loading the Counter and setting
reading/writing least significant byte (LSB) only.
of 10, Hex is written to the Counter.
the least significant byte. The upper number is the most
significant byte. Since the Counter is programmed to read/write
LSB only, the most significant byte cannot be read.
GATE
GATE
GATE
OUT
OUT
OUT
CLK
CLK
CLK
WR
WR
WR
CW = 10
CW = 12
CW = 10
N
N
N
N
N
N
LSB = 4
LSB = 3
LSB = 3
N
N
N
FIGURE 17. MODE 0
N
N
N
0
4
0
3
0
3
LSB = 2
0
3
0
2
0
2
0
2
0
2
0
1
0
1
0
2
0
2
0
0
0
1
0
1
FF
FF
0
0
0
0
FF
FE
FF
FF
FF
FF