HS1-82C54RH-8 Intersil, HS1-82C54RH-8 Datasheet - Page 13

• Manufacturer Part Number: HS1-82C54RH-8
• Manufacturer: Intersil

Specifications of HS1-82C54RH-8

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Mode 3: Square Wave Mode
Mode 3 is typically used for Baud rate generation. Mode 3 is
similar to Mode 2 except for the duty cycle of OUT. OUT will
initially be high. When half the initial count has expired, OUT
goes low for the remainder of the count. Mode 3 is periodic;
the sequence above is repeated indefinitely. An initial count
of N results in a square wave with a period of N CLK cycles.
GATE = 1 enables counting; GATE = 0 disables counting. If
GATE goes low while OUT is low, OUT is set high
immediately; no CLK pulse is required. A trigger reloads the
Counter with the initial count on the next CLK pulse. Thus
the GATE input can be used to synchronize the
Counter.After writing a Control Word and initial count, the
Counter will be loaded on the next CLK pulse. This allows
the Counter to be synchronized by software also.
Writing a new count while counting does not affect the
current counting sequence. If a trigger is received after
writing a new count but before the end of the current half-
cycle of the square wave, the Counter will be loaded with the
new count on the next CLK pulse and counting will continue
from the new count. Otherwise, the new count will be loaded
at the end of the current half-cycle.
Mode 3 is implemented as follows:
EVEN COUNTS: OUT is initially high. The initial count is
loaded on one CLK pulse and then is decremented by two
on succeeding CLK pulses. When the count expires, OUT
changes value and the Counter is reloaded with the initial
count. The above process is repeated indefinitely.
ODD COUNTS: OUT is initially high. The initial count is
loaded on one CLK pulse, decremented by one on the next
CLK pulse, and then decremented by two on succeeding
CLK pulses. When the count expires, OUT goes low and the
Counter is reloaded with the initial count. The count is
decremented by three on the next CLK pulse, and then by
two on succeeding CLK pulses.When the count expires,
OUT goes high again and the Counter is reloaded with the
initial count. The above process is repeated indefinitely. So
for odd counts, OUT will be high for (N + 1)/2 counts and low
for (N-1)/2 counts.
37. Numbers below diagrams are count values. The lower number is
38. N stands for an undefined count.
39. Vertical lines show transitions between count values.
the least significant byte. The upper number is the most
significant byte. Since the Counter is programmed to read/write
LSB only, the most significant byte cannot be read.
FIGURE 19. MODE 2
13
HS-82C54RH
Mode 4: Software Triggered Mode
OUT will be initially high. When the initial count expires, OUT
will go low for one CLK pulse then go high again.The
counting sequence is “Triggered” by writing the initial count.
GATE = 1 enables counting; GATE = 0 disables counting.
GATE has no effect on OUT.
After writing a Control Word and initial count, the Counter will
be loaded on the next CLK pulse. This CLK pulse does not
decrement the count, so for an initial count of N, OUT does
not strobe low until N + 1 CLK pulses after the initial count is
written.
If a new count is written during counting, it will be loaded on
the next CLK pulse and counting will continue from the new
count. If a two-byte count is written, the following happens:
This allows the sequence to be “retriggered” by software.
OUT strobes low N + 1 CLK pulses after the new count of N
is written.
Mode 5: Hardware Triggered Strobe
(Retriggerable)
OUT will initially be high. Counting is triggered by a rising
edge of GATE. When the initial count has expired, OUT will
go low for one CLK pulse and then go high again.
After writing the Control Word and initial count, the Counter
will not be loaded until the CLK pulse after a trigger. This
CLK pulse does not decrement the count, so for an initial
count of N, OUT does not strobe low until N + 1 CLK pulses
after trigger.
A trigger results in the Counter being loaded with the initial
count on the next CLK pulse. This allows the counting
sequence to be regretted. OUT strobes low N + 1 CLK
pulses after any new trigger. GATE has no effect on the state
of OUT.
If a new count is written during counting, the current
counting sequence will not be affected. If a trigger occurs
after the new count is written but before the current count
expires, the Counter will be loaded with the new count on the
next CLK pulse and counting will continue from there.
1. Writing the first byte has no effect on counting.
2. Writing the second byte allows the new count to be loaded
on the next CLK pulse.