LU82551IT 860607 Intel, LU82551IT 860607 Datasheet - Page 22

• Manufacturer Part Number: LU82551IT 860607
• Manufacturer: Intel

Specifications of LU82551IT 860607

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Compliant

82551IT — Networking Silicon
5.2
5.2.1
5.2.1.1
16
Table 10. Initialization Effects
PCI Interface
Bus Operations
After configuration, the 82551IT is ready for its normal operation. As a Fast Ethernet Controller,
the role of the 82551IT is to access transmitted data or deposit received data. In both cases the
82551IT, as a bus master device, will initiate memory cycles by way of the PCI bus.
To perform these actions, the 82551IT is controlled and examined by the CPU through its control
and status structures and registers. Some of these structures reside in the 82551IT and some reside
in system memory. For access to the 82551IT’s Control/Status Registers (CSR), the 82551IT acts
as a slave device. The 82551IT serves as a slave also while the CPU accesses its 128 KB Flash
buffer or its EEPROM.
Section 5.2.1.1
82551IT operation as a bus master (initiator) in
Bus Slave Operation
The 82551IT serves as a target device in the following cases:
The CSR and the 1 MB Flash buffer are considered by the 82551IT as totally separated memory
spaces. The 82551IT provides separate Base Address Registers (BARs) in the configuration space
to distinguish between them. The size of the CSR memory space is 4 KB in the memory space and
64 bytes in the I/O space. The 82551IT treats accesses to these memory spaces differently.
Power
management
event reset
Statistic
counters reset
Sampling of
configuration
input pins
•
•
•
•
•
•
CPU accesses to the 82551IT System Control Block (SCB) Control/Status Registers (CSR)
CPU accesses to the EEPROM through its CSR
CPU accesses to the 82551IT PORT address through the CSR
CPU accesses to the MDI control register in the CSR
CPU accesses to the Flash control register in the CSR
CPU accesses to the 128 KB Flash
describes the 82551IT slave operation. It is followed by a description of the
Internal
POR
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ALTRST#
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Clear only
auxiliary
present
power
RST#
if no
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Section
ISOLATE#
Clear only
auxiliary
present
power
if no
5.2.1.2.
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Transition
D3 to D0
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Software
Reset
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Datasheet
Selective
Reset
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