DP83932CVF25 National Semiconductor, DP83932CVF25 Datasheet - Page 67

• Manufacturer Part Number: DP83932CVF25
• Manufacturer: National Semiconductor

Specifications of DP83932CVF25

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Mounting: Surface Mount
• Pin Count: 132
• Lead Free Status / RoHS Status: Not Compliant

ure 5-25 ) The host system indicates its intentions to use
5 0 Bus Interface
5 4 8 On-Chip Memory Arbiter
For applications which share the buffer memory area with
the host system (shared-memory applications) the SONIC
provides a fast on-chip memory arbiter for efficiently resolv-
ing accesses between the SONIC and the host system ( Fig-
the shared-memory by asserting Memory Request (MREQ)
The SONIC will allow the host system to use the shared
memory by acknowledging the host system’s request with
Slave and Memory Acknowledge (SMACK) Once SMACK
is asserted the host system may use the shared memory
freely The host system gives up the shared memory by
deasserting MREQ
MREQ is clocked in on the falling edge of bus clock and is
double synchronized internally to the rising edge SMACK is
asserted on the falling edge of a Ts bus cycle If the SONIC
is not currently accessing the memory SMACK is asserted
immediately after MREQ was clocked in If however the
SONIC is accessing the shared memory it finishes its cur-
rent memory transfer and then issues SMACK SMACK will
be asserted one bus clock minimum to five bus clocks maxi-
mum after MREQ is clocked in Since MREQ is double syn-
chronized it is not necessary to meet its setup time Meet-
ing the setup time for MREQ will however guarantee that
SMACK is asserted one to five bus clocks after the current
bus clock SMACK will deassert within one bus clock after
MREQ is deasserted The SONIC will then finish its master
operation if it was using the bus previously
If the host system needs to access the SONIC’s registers
instead of shared memory CS would be asserted instead of
MREQ Accessing the SONIC’s registers works almost ex-
actly the same as accessing the shared memory except that
the SONIC goes into a slave cycle instead of going idle See
Section 5 4 7 for more information about how register ac-
cesses work
Note 1 The successive assertion of CS and MREQ must be separated by
Note 2 The number of bus clocks between MREQ being asserted and the
Note 3 The way in which SMACK is asserted due to CS is not the same as
Note 4 In Motorola mode if a bus master uses the MREQ to request the
at least two bus clocks Both CS and MREQ must not be asserted
concurrently
assertion of SMACK when the SONIC is in Master Mode is 5 bus
clocks assuming there were no wait states in the Master Mode
access Wait states will increase the time for SMACK to go low by
the number of wait states in the cycle (the time will be 5
number of wait states)
the way in which SMACK is asserted due to MREQ SMACK goes
low as a direct result of the assertion of MREQ whereas for CS
SAS must also be driven low (BMODE
before SMACK will be asserted This means that when SMACK is
asserted due to MREQ SMACK will remain asserted until MREQ is
deasserted Multiple memory accesses can be made to the shared
memory without SMACK ever going high When SMACK is asserted
due to CS however SMACK will only remain low as long as SAS is
also low (BMODE
multiple register accesses to the SONIC because SAS must toggle
for each register access This is an important difference to consider
when designing shared memory designs
bus from the SONIC care should be taken to isolate the DSACK0 1
from the bus (e g use TRI-STATE buffers) because the DSACK0 1
will be driven by the SONIC even after the SONIC has given up the
bus
e
1) SMACK will not remain low throughout
(Continued)
e
1) or high (BMODE
a
e
the
0)
67
5 4 9 Chip Reset
The SONIC has two reset modes a hardware reset and a
software reset The SONIC can be hardware reset by as-
serting the RESET pin or software reset by setting the RST
bit in the Command Register (Section 4 3 1) The two reset
modes are not interchangeable since each mode performs
a different function
during a hardware reset Bits 15-12 of the DCR2 are unknown until written
to All other bits in these two registers are unchanged
bits are unchanged
After power-on the SONIC must be hardware reset before it
will become operational This is done by asserting RESET
for a minimum of 10 transmit clocks (10 ethernet transmit
clock periods TXC) If the bus clock (BSCK) period is great-
er than the transmit clock period RESET should be assert-
ed for 10 bus clocks instead of 10 transmit clocks A hard-
ware reset places the SONIC in the following state (The
registers affected are listed in parenthesis See Table 5-4
and Section 4 3 for more specific information about the reg-
isters and how they are affected by a hardware reset Only
those registers listed below and in Table 5-4 are affected by
a hardware reset )
1
2
3
4
5
6
7
8
9
10 All interrupt status bits are reset (ISR)
11 The Extended Bus Mode is disabled (DCR)
12 HOLD will be asserted deasserted from the falling clock
Bits 15 and 13 of the DCR and bits 4 through 0 of the DCR2 are reset to a 0
Bits LB1 LB0 and BRD are reset to a 0 during hardware reset All other
Command
Data Configuration
(DCR and DCR2)
Interrupt Mask
Interrupt Status
Transmit Control
Receive Control
End Of Buffer Count
Sequence Counters
CAM Enable
TABLE 5-4 Internal Register Content after RESET
Receiver and Transmitter are disabled (CR)
The General Purpose timer is halted (CR)
All interrupts are masked out (IMR)
The NCRS and PTX status bits in the Transmit Control
Register (TCR) are set
The End Of Byte Count (EOBC) register is set to 02F8h
(760 words)
Packet and buffer sequence number counters are set to
zero
All CAM entries are disabled The broadcast address is
also disabled (CAM Enable Register and the RCR)
Loopback operation is disabled (RCR)
The latched bus retry is set to the unlatched mode
(DCR)
edge (DCR2)
Register
Hardware
0094h
0000h
0000h
0101h
02F8h
0000h
0000h
Reset
Contents after Reset
0094h 00A4h
unchanged
unchanged
unchanged
unchanged
unchanged
unchanged
unchanged
unchanged
Software
Reset