DP83932CVF25 National Semiconductor, DP83932CVF25 Datasheet - Page 83

• Manufacturer Part Number: DP83932CVF25
• Manufacturer: National Semiconductor

Specifications of DP83932CVF25

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Mounting: Surface Mount
• Pin Count: 132
• Lead Free Status / RoHS Status: Not Compliant

7 0 AC and DC Specifications
Note 1 For successive read operations MRW remains high
Note 2 Meeting the setup time for DSACK0 1 or STERM guarantees that the SONIC will terminate the memory cycle 1
sampled or 1 cycle after STERM was sampled T2 states will be repeated until DSACK0 1 or STERM are sampled properly in a low state If the SONIC samples
DSACK0 1 or STERM low during the T1 or first T2 state respectively the SONIC will finish the current access in a total of two bus clocks instead of three (assuming
that programmable wait states are set to 0) DSACK0 1 are asynchronously sampled and STERM is synchronously sampled
Number
T9
T11a
T11c
T12a
T12c
T13a
T13b
T14
T15a
T16
T17
T19
T22
T23a
T24a
T28
T30
T30a
T31
T31a
BSCK to Address Valid
BSCK to AS Low
BSCK to ECS Low
BSCK to AS High
BSCK to ECS High
BSCK to DS Low
BSCK to DS High
AS Low Width
AS High Width
Read Data Strobe High Width
Read Data Strobe Low Width
Address Hold Time from AS
Address Valid to AS
Read Data Setup Time to BSCK
Read Data Hold Time from BSCK
BSCK to MRW (Read) Valid (Note 1)
DSACK0 1 Setup to BSCK (Note 2)
STERM Setup to BSCK (Note 2)
DSACK0 1 Hold from BSCK
STERM Hold from BSCK
Parameter
(Continued)
Min
44
45
45
40
18
3
9
5
5
5
5
9
8
20 MHz
83
Max
26
17
19
17
19
16
16
26
Min
34
35
35
30
14
3
6
4
5
4
4
8
7
25 MHz
Max
24
15
17
15
17
14
14
24
Min
bus clocks after DSACK0 1 were
24
25
25
20
10
3
2
3
5
3
3
7
6
33 MHz
Max
22
13
15
13
15
12
12
22
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns