SCD243110QCD Intel, SCD243110QCD Datasheet
SCD243110QCD
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SCD243110QCD Summary of contents
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... The CD2431 is based on a proprietary on-chip RISC processor that performs all time-critical, low-level tasks that are otherwise performed by the host system. The CD2431 boosts system efficiency with on-chip DMA, on-chip FIFOs, intelligent vectored interrupts, and intelligent protocol processing. The on-chip DMA controller provides ‘fire-and- forget’ ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel’s website at http://www.intel.com. ...
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Contents 1.0 Features ......................................................................................................................... 9 1.1 Benefits ...............................................................................................................11 1.2 CD2XXX Family Compatibility.............................................................................11 2.0 Conventions ...............................................................................................................13 3.0 Pin Information 3.1 Pin Diagram — CD2431......................................................................................15 3.2 Pin Functions — CD2431....................................................................................16 3.3 Pin Descriptions ..................................................................................................16 4.0 Register Table 4.1 Memory Map .......................................................................................................20 4.1.1 ...
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CD2431 — Advanced Multi-Protocol Communications Controller 5.4.1 Bus Acquisition Cycle............................................................................. 43 5.4.2 DMA Data Transfer ................................................................................ 44 5.4.3 Bus Error Handling................................................................................. 45 5.4.4 A and B Buffers and Chaining ................................................................ 45 5.4.5 Transmit DMA Transfer .......................................................................... 46 5.4.6 Synchronous Transmitter ...
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Transmit Interrupt Service Routine......................................................................88 8.0 Detailed Register Descriptions 8.1 Global Registers..................................................................................................89 8.1.1 Global Firmware Revision Code Register (GFRCR) ..............................89 8.1.2 Channel Access Register (CAR) ............................................................89 8.2 Option Registers..................................................................................................90 8.2.1 Channel Mode Register (CMR) ..............................................................90 8.2.2 Channel Option Register 1 ...
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CD2431 — Advanced Multi-Protocol Communications Controller 9.3 AC Electrical Characteristics ............................................................................. 165 10.0 Package Specifications 11.0 Ordering Information Index ....................................................................................................................................... 177 Bit Index ....................................................................................................................................... 183 6 ....................................................................................... 174 ............................................................................................ 175 Datasheet ...
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Figures 1 Functional Block Diagram ...................................................................................11 2 Host Read Cycle .................................................................................................35 3 Host Write Cycle..................................................................................................36 4 Interrupt Acknowledge Cycle...............................................................................38 5 Bus Acquisition Cycle..........................................................................................44 6 Data Transfer Timing...........................................................................................45 7 Transmitter A and B Buffers ................................................................................48 8 Receiver A and B Buffers ...
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CD2431 — Advanced Multi-Protocol Communications Controller Revision History Revision Date 1.0 May 2001 8 Description Initial release. Datasheet ...
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Features • Four full-duplex multi-protocol channels, each running up to 134.4 kbits/second (with CLK = 35 MHz) • Supports async, async-HDLC (high-level data link control), and HDLC/SDLC (synchronous data link control; non-multidrop) on all channels • 32-bit address, 16-bit ...
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CD2431 — Advanced Multi-Protocol Communications Controller — In-band (software) via XON/XOFF — Out-of-band (hardware flow control) via RTS/CTS and DTR/DSR — Line break detection and generation — Special-character and character-range recognition and transmission — Transmit delay • 8-bit ...
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Figure 1. Functional Block Diagram HOST BUS INTERFACE LOGIC HOST INTERFACE ON-CHIP DMA CONTROLLER AND INTERFACE LOGIC 1.1 Benefits • Substantially reduced host CPU overhead means more channels and faster overall throughput. • No time-critical host software enables faster, easier ...
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CD2431 — Advanced Multi-Protocol Communications Controller Features Serial data rate (kbits/second) Number of modem leads (per channel, including RxD and TxD) On-chip timers UNIX character processing In-band Rx flow control Special character Tx and recognition Package System interface Pin compatibility ...
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Conventions This section lists abbreviations and acronyms used in this datasheet. Abbreviations Symbol Kbit kbits/sec. kbps Kbyte kbytes/sec. kHz k Mbyte MHz The use of ‘tbd’ indicates values that ...
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CD2431 — Advanced Multi-Protocol Communications Controller Acronyms Acronym AC alternating current BRG bit rate generation bisync byte synchronous CMOS complementary metal-oxide semiconductor CRC cyclic redundancy chack DC direct current DCE data communication equipment DMA direct-memory access DPLL digital phase-locked loop ...
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Pin Information 3.1 Pin Diagram — CD2431 RXCIN[3] 51 TXCIN[3] 52 DSR*[0] 53 CTS*[0] 54 TXCOUT/DTR*[0] 55 RTS*[0] 56 DSR*[1] 57 CTS*[1] 58 TXCOUT/DTR*[1] 59 RTS*[1] 60 DSR*[2] 61 GND 62 CTS*[2] 63 TXCOUT/DTR*[2] 64 RTS*[2] 65 DSR*[3] 66 ...
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CD2431 — Advanced Multi-Protocol Communications Controller 3.2 Pin Functions — CD2431 A [0-7] A/D [0-15] CLK CS* AS* DS* R/W* DTACK* SIZ [0-1] BUSCLK BERR* RESET* TEST ADLD* AEN* DATDIR* DATEN* BYTESWAP IACKIN* IACKOUT* IREQ*[1-3] BR* BGIN* BGOUT* BGACK* 3.3 ...
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Table 1. Pin Descriptions (Sheet Pin Symbol Type Number CS* 1 AS* 14 I/O (TS) DS* 15 I/O (TS) R/W* 13 I/O (TS) DTACK* 16 I/O (OD) SIZ[0– I/O (TS) IACKIN* 17 IACKOUT* 19 IREQ*[1–3] ...
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CD2431 — Advanced Multi-Protocol Communications Controller Table 1. Pin Descriptions (Sheet Pin Symbol Type Number BGACK* 12 I/O (OD) BERR* 100 A[7:0] 71–78 I/O (TS) 80, 81, 83, A/D[15:0] 84, 86–95, I/O (TS) 97, 98 ADLD* 29 ...
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... A/D[8–15] when A[0] is high. When BYTESWAP is low, bytes are transferred on A/D[8–15] when A[0] is low, and A/D[0–7] when A[0] is high. A different register map is used, depending on the state of this pin. Byteswap Byte Alignment 0 Motorola byte alignment 1 Intel byte alignment – POWER – GROUND Description processor systems ...
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... The following notes are applicable for NOTES: 1. Address mode G: Global register — one set is always accessible. Address mode P: Per-Channel register — two sets, one per channel, accessible by CAR or interrupt context. 2. INT = address for Intel -style processor. 3. MOT = address for Motorola -style processor. 4.1.2 Option Registers Name ...
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Name Description COR6 Channel Option Register 6 COR7 Channel Option Register 7 SCHR1 Special Character Register 1 SCHR2 Special Character Register 2 SCHR3 Special Character Register 3 SCHR4 Special Character Register 4 SCRl Special Character Range low SCRh Special Character ...
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CD2431 — Advanced Multi-Protocol Communications Controller 4.1.4 Channel Command and Status Registers Name Description CCR Channel Command Register STCR Special Transmit Command Register CSR Channel Status Register MSVR-RTS Modem Signal Value Registers MSVR-DTR 4.1.5 Interrupt Registers Name Description LIVR Local ...
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Name Description TFTC Transmit FIFO Transfer Count TDR Transmit Data Register TEOIR Transmit End of Interrupt Register 4.1.5.3 Modem Interrupt Registers Name Description MPILR Modem Priority Interrupt Level Register MIR Modem Interrupt Register MISR Modem (/Timer) Interrupt Status Register MEOIR ...
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CD2431 — Advanced Multi-Protocol Communications Controller 4.1.6.2 DMA Transmit Registers Name Description ATBADRL A Transmit Buffer Address Lower ATBADRU A Transmit Buffer Address Upper BTBADRL B Transmit Buffer Address Lower BTBADRU B Transmit Buffer Address Upper ATBCNT A Transmit Buffer ...
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Register Definitions 4.2.1 Global Registers Global Firmware Revision Code Register (GFRCR) Channel Access Register (CAR 4.2.2 Option Registers Channel Mode Register (CMR) RxMode TxMode 0 Channel Option Register 1 (COR1) HDLC Mode AFLO ClrDet AdMde1 Asynchronous ...
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CD2431 — Advanced Multi-Protocol Communications Controller MNP 4 Mode Stop2 FCSApd RxChk HDLC Mode sndpad Alt1 FCSPre Asynchronous Mode EDCDE RngDE FCT SLIP Mode Stop2 0 Channel Option Register 4 (COR4) DSRzd CDzd CTSzd Channel Option Register 5 (COR5) DSRod ...
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Receive Frame Address Registers Receive Frame Address Register 1 (RFAR1) Receive Frame Address Register 2 (RFAR2) Receive Frame Address Register 3 (RFAR3) Receive Frame Address Register 4 (RFAR4) CRC Polynomial Select Register (CPSR Transmit Special Mapped Characters ...
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CD2431 — Advanced Multi-Protocol Communications Controller 4.2.4 Channel Command and Status Registers Channel Command Register (CCR) 0 ClrCh InitCh 1 ClrT1 ClrT2 Special Transmit Command Register (STCR) Async-HDLC/PPP Mode 0 Abort SLIP/MNP 4 Mode 0 Abort Asynchronous and HDLC Modes ...
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Interrupt Registers Local Interrupt Vector Register (LIVR Interrupt Enable Register (IER) Mdm 0 RET Local Interrupting Channel Register (LICR Interrupt Stack Register (STK) CLvl [1] MLvl [1] TLvl [1] 4.2.5.1 Receive Interrupt Registers ...
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CD2431 — Advanced Multi-Protocol Communications Controller Receive Interrupt Status Register high (RISRh) Berr EOF EOB Receive FIFO Output Count (RFOC Receive Data Register (RDR Receive End of Interrupt Register (REOIR) Asynchronous and HDLC Modes TermBuff ...
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Modem/Timer Interrupt Registers Modem Priority Interrupt Level Register (MPILR) Modem Interrupt Register (MIR) Men Mact Meo Modem (/Timer) Interrupt Status Register (MISR) DSRChg CDChg CTSChg Modem End of Interrupt Register (MEOIR SetTm2 4.2.6 DMA Registers DMA Mode ...
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CD2431 — Advanced Multi-Protocol Communications Controller Receive Current Buffer Address Lower (RCBADRL) Receive Current Buffer Address Upper (RCBADRU) 4.2.6.2 DMA Transmit Registers A Transmit Buffer Address Lower (ATBADRL) A Transmit Buffer Address Upper (ATBADRU) B Transmit Buffer Address Lower (BTBADRL) ...
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Receive Time-Out Period Register high (RTPRh) General Timer 1 (GT1) General Timer 1 low (GT1l) General Timer 1 high (GT1h) General Timer 2 (GT2) Transmit Timer Register (TTR) Datasheet Advanced Multi-Protocol Communications Controller — CD2431 Binary Value, bits 15:8 27 ...
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CD2431 — Advanced Multi-Protocol Communications Controller 5.0 Functional Description 5.1 Host Interface The CD2431 is a synchronous device with an asynchronous bus interface. A stable input clock is required on the CLK pin — nominally 33 MHz. The CLK is ...
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Figure 2. Host Read Cycle CS* DS* R/W* A/D[15:0] A[7:0], SIZ[1:0] DTACK* DATEN* DATDIR* Datasheet Advanced Multi-Protocol Communications Controller — CD2431 DOUT 35 ...
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CD2431 — Advanced Multi-Protocol Communications Controller Figure 3. Host Write Cycle CS* DS* R/W* A/D[15:0] A[7:0], SIZ[1:0] DTACK* DATEN* DATDIR* 5.1.2 Byte and Word Transfers Data can be moved to and from the CD2431 in either byte or word transfers. ...
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Contexts and Channels The registers in the CD2431 are grouped into Global, Virtual, and four sets of Per-Channel registers. The CD2431 is normally in the background context, where the CAR (Channel Access register) selects the channel number for the ...
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CD2431 — Advanced Multi-Protocol Communications Controller Figure 4. Interrupt Acknowledge Cycle IREQn* IACKIN* DS* R/W*, CS* A/D[15:0] A[7:0] DTACK* DEN* DATDIR* * INTERRUPT VECTOR IS ALWAYS ON A/D[7:0] 5.2.3 Groups and Types There are two general reasons for the CD2431 ...
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Table 2. Transmit and Receive Interrupt Service Requests Interrupt Cause ASYNC Receive Good Data • Break detect • Framing error • Parity error • Receive timeout, no data • Special character match • Transmitter empty • Tx FIFO threshold • ...
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CD2431 — Advanced Multi-Protocol Communications Controller Transmit Interrupt register Lowest priority: Modem Interrupt register 5.2.4.2 Systems with Interrupt Controllers Some systems use an interrupt controller that supplies its own vector during the interrupt acknowledge cycle. To function properly, the CD2431 ...
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When an interrupt request line is asserted, the Fair bit for that type of interrupt on the asserting device is cleared. The Fair bit remains cleared until the interrupt line returns to a high state. The CD2431 does not assert ...
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CD2431 — Advanced Multi-Protocol Communications Controller 5.3.4 Timers in Synchronous Protocols In synchronous protocols, the timers have no special significance for the CD2431; they are available to support the protocols. They are started by host commands or by interrupts generated ...
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The CD2431 can perform DMA operations in any of the supported line protocols. A special Append mode feature can reduce host CPU overhead for asynchronous datastreams. DMA operations are channel- and direction-specific. In each channel, either the transmitter and the ...
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CD2431 — Advanced Multi-Protocol Communications Controller Figure 5. Bus Acquisition Cycle BR* BGIN* BGACK* Another component owns the bus and gives it up here. The CD2431 owns the bus at this point. 5.4.2 DMA Data Transfer After the CD2431 acquires ...
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Figure 6. Data Transfer Timing ADLD* AEN* DATDIR* AS* R/W* DS* DTACK* 5.4.3 Bus Error Handling When a bus error is detected during a DMA sequence, the CD2431 terminates the current bus cycle and relinquishes the bus. Any data transfer ...
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CD2431 — Advanced Multi-Protocol Communications Controller The CD2431 keeps track of which buffer ( used next in the status bits — Ntbuf for transmit and Nrbuf for receive. The relationship between the 2431own bit and ...
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Chain Mode Transfer In Chain mode, the frame should be complete in buffers in memory before transmission is started. The Append Status bit should not be set; the Start of Frame bit must be set to begin transmission, and the ...
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CD2431 — Advanced Multi-Protocol Communications Controller Figure 7. Transmitter A and B Buffers CD2431 Transmit DMA Registers ATBADR (32) ATBCNT (16) ATBSTS (8) (Status register) TABADR (32) (Currently using Buffer A) BTBADR (32) BTBCNT (16) BTBSTS (8) (Status register) NOTE: ...
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The CD2431 optionally interrupts the host, with EOF and EOB in the TISR both set to indicate that the transmission is complete and there was no chaining. Example 2 Transmit out of channel 0 and chain three buffers into ...
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CD2431 — Advanced Multi-Protocol Communications Controller 15. When the CD2431 completes transmission, any necessary CRCs and ending frame delimiters are transmitted. 16. The CD2431 optionally interrupts the host with EOF and EOB bits set (TISR[6:5]) to indicate that the transmission ...
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Receiver A and B Buffers In the Figure 8, buffers A and B are contained in RAM external to the CD2431. All others (DMABSTS, ARBADR, ARBCNT, ARBSTS, RCBADR, BRBADR, BRBCNT, and BRBSTS) are inside the CD2431. Figure 8. Receiver A ...
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CD2431 — Advanced Multi-Protocol Communications Controller 6. The CD2431 sets the EOB and EOF bits. This notifies the host that the end of the buffer and frame have been reached. The CD2431 also clears the 2431own bit to return the ...
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The CD2431 optionally interrupts the host with the EOF and EOB bits set (RISRh[6:5]) to indicate that the received frame is complete, and this was the last link in the chain. 5.4.8 Transmit DMA Transfer The CD2431 contains two ...
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CD2431 — Advanced Multi-Protocol Communications Controller Figure 9. DMA Transmit Buffer Selection Update Descriptor and Set 2431own No More Data to Send ? 54 Start Read DMABSTS to Determine Next Transmit Buffer (NtBuf) Next Buffer 0 1 2431own Bit ? ...
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Append Mode The Append mode reduces the CPU overhead required to provide asynchronous terminal echoing functionality; this is also necessary for any similar application that involves an unpredictable datastream. The A buffer can be set into Append mode by ...
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CD2431 — Advanced Multi-Protocol Communications Controller The CPU has the following five options: 1. Terminate the buffer. 2. Discard the exception. 3. Terminate the buffer and discard the exception. 4. Continue from the current position in the buffer. 5. Leave ...
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To retry the buffer from the failure point, the CPU should set the 2431own bit in the A/BRBSTS register. The CPU should not set the TermBuff bit when writing to REOIR at the end of the interrupt, this causes the ...
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CD2431 — Advanced Multi-Protocol Communications Controller The receive bit rate generator can also be programmed to act as a DPLL. In that mode, the clock select and divisor are programmed near as possible to the nominal receive ...
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Figure 10. BRG and DPLL System Clock 8 Clk 0 32 Clk 1 128 Clk 2 512 Clk 3 2048 Clk 4 RXCIN or TXCIN RX bit clk (for TX BRG only) Receive Clock Option Register (RCOR) TLVal res dpllEn ...
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CD2431 — Advanced Multi-Protocol Communications Controller Table 4. Clock Source Select (Sheet ClkSel2 ClkSel1 Table 5. Bit Rate Constants, CLK = 20 MHz Bit Rate 50 110 150 300 600 1200 ...
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Table 6. Bit Rate Constants, CLK = 25 MHz (Sheet Bit Rate 19200 38400 56000 64000 76800 1.All divisors are in hexadecimal. Table 7. Bit Rate Constants, CLK = 30 MHz Bit Rate 110 150 300 600 ...
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CD2431 — Advanced Multi-Protocol Communications Controller Table 8. Bit Rate Constants, CLK = 35 MHz (Sheet Bit Rate 3600 4800 7200 9600 19200 38400 56000 64000 76800 115200 12800 134400 1.All divisors are in hexadecimal. Transmit and ...
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The equation to compute the divisor value is: rate divisor Figure 11. Data Encoding Figure 12. Transmit Data With External Clock In NOTE: When using the external receive clock in Receive mode, data is sampled on the low-to-high going edge ...
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CD2431 — Advanced Multi-Protocol Communications Controller Table 9. Data Clock Selection Using External Clock Bit Rate 50 110 150 300 600 1200 2400 3600 4800 7200 9600 19200 38400 56000 64000 76800 115200 128000 5.6 Hardware Configurations To demultiplex the ...
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Interface to a 32-Bit Data Bus To interface to a 32-bit data bus, two 16-bit data buffers must be used to isolate the CD2431 A/ D[15:0] pins from either half of the 32-bit bus. The A[1] address pin determines ...
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CD2431 — Advanced Multi-Protocol Communications Controller CD2431 RXD TXD RTS* CTS* DSR* TXCOUT/DTR* RXCIN TXCIN RXCOUT CD* The following table shows the recommended DCE (data communications equipment) connections between the CD2431 and RS-232C standard interfaces. CD2431 RXD TXD RTS* CTS* ...
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Protocol Processing 6.1 HDLC Processing 6.1.1 FCS (Frame Check Sequence) The FCS is a 16-bit standard computation used in HDLC, and defined in ISO 3309. This FCS algorithm is the same that is used with the synchronous HDLC operation ...
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CD2431 — Advanced Multi-Protocol Communications Controller When end-of-frame status is passed to the CD2431 by the TEOIR or the A/BTBSTS, and the remaining data transmitted, the CRC and a closing flag are appended to the frame new frame ...
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PPP (Point-to-Point Protocol) Mode 6.2.1 Character Format The PPP mode uses the async-HDLC character format, which is fixed as one start bit, eight data bits, and one stop bit. There is no parity bit. The character format is as ...
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CD2431 — Advanced Multi-Protocol Communications Controller 6.2.4 Transparency Transparency means that there is a protocol method to prevent confusion and ambiguity between control characters and data characters in the frame. For PPP mode, there is a control-escape mechanism. Specific characters ...
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Definition of a Valid Frame This section discusses valid frames from the viewpoint of the CD2431 devices. All characters are formatted as in the standard async-HDLC format shown in a channel is placed in the PPP mode, that channel ...
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CD2431 — Advanced Multi-Protocol Communications Controller Option map32 (ATBSTS) (BTBSTS) npad3 (COR3) TxGen (COR3) frame (STCR) 6.2.6.3 Transmission of Abort When commanded through a bit in the STCR (Special Transmit Command register), the device ends the transmission ...
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Option RxChk (COR3) RTPR 6.3 SLIP Processing Note: SLIP, MNP 4, and Automatic In-Band Flow Control modes are only available on Revision B and later devices. 6.3.1 Framing As defined in the original implementation, SLIP frames end with an ‘END’ ...
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CD2431 — Advanced Multi-Protocol Communications Controller 6.3.2 Debugging Aids For debug purposes, the CD2431 can send the sequence ‘ESC’, ‘END’, by the STCR (Special Transmit Command register). This is intended as an abort frame function. The STCR also has a ...
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Both versions escape the escape character (in SHCR2) by duplicating appears within the data stream. 6.4.2 MNP 4/ARAP FCS (Frame Check Sequence) Calculation Both versions use the ( with remainder equal to 0x1D0F. The frame body and ...
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CD2431 — Advanced Multi-Protocol Communications Controller When in-band flow control is enabled (TxIBE = 1) and an XOFF character is received, the channel stops transmission after the current character in the transmit shift register and the current character in the ...
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For example, it does not transmit an XON simply because the number of characters is below the threshold; it only does had previously sent an XOFF due to the threshold being ...
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CD2431 — Advanced Multi-Protocol Communications Controller For example, if the CD2431 is designed to be DCE and automatic out-of-band flow control is desired, connect the DTR pin to the remote CTS input. If the CD2431 used as ...
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When the host commands a special character transmission, the channel completes transmitting any characters in the Transmit Shift register and Transmit Holding register, and then transmit the special character sequence. Any other characters awaiting transmission in the FIFO or through ...
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CD2431 — Advanced Multi-Protocol Communications Controller Table 14. SCdet[x] Settings SCdet2 SCdet1 6.5.7 UNIX Support Features The COR6 provides several functions useful for UNIX TTY drivers, to further ...
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Figure 19. CD2431 Receive Character Processing Character Received N Error? Y ISTRIP COR7[7] Y FCErr COR7[5] N LNE COR7[6] Previous Y CHAR = LNXT N ISTRIP COR7[7] N SCDE COR3[4] N ESCDE COR3[ Datasheet Advanced Multi-Protocol Communications Controller ...
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CD2431 — Advanced Multi-Protocol Communications Controller Figure 19. CD2431 Receive Character Processing (Continued CHAR = BREAK Y Process Break Options IgnBrk NBrkInt Done 82 COR6[4:3] Action Exception interrupt Discard character Replace with ...
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Figure 19. CD2431 Receive Character Processing (Continued) B RNGDE COR3[6] N CR/NL Y Options COR6[ CHAR = FF N Datasheet Advanced Multi-Protocol Communications Controller — CD2431 SCRl< Exception CHAR< Interrupt SCRh N Y Discard CHAR = ...
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CD2431 — Advanced Multi-Protocol Communications Controller 7.0 Programming Examples This section provides some examples of the CD2431 programming. Included are examples of global and per-channel initialization, and two interrupt service routines. The code is written in Borland Turbo C . ...
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Global Initialization The following code segment is an example of global initialization. The host waits for a hardware reset, determined by a non-zero value in the GFRCR. A ‘RESET ALL’ command is sent to the CD2431 by the CCR. ...
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CD2431 — Advanced Multi-Protocol Communications Controller 7.2 Async Interrupt Setup Example This section provides a code example for an asynchronous channel running at 19,200 bps, with 8 bits/character, 1 Stop bit, and no parity. The sample program enables In-Band Flow ...
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Receive DMA Interrupt Service Routine The following code example shows an interrupt service routine for the CD2431 in DMA mode. The buffer class array ib used for notational convenience, and its exact implementation is user- defined. The ...
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CD2431 — Advanced Multi-Protocol Communications Controller 7.5 Transmit Interrupt Service Routine The following code example is a transmit interrupt service handler example. When using a synchronous protocol, transmitters must declare an end of frame if an underrun occurs. If the ...
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... Bits 1:0 Channel number Datasheet Advanced Multi-Protocol Communications Controller — CD2431 Bit 4 Bit 3 Firmware revision code Bit 4 Bit 3 Reserved Intel Hex Address: x’82 Motorola Hex Address: x’81 Bit 2 Bit 1 Bit 0 Intel Hex Address: x’EC Motorola Hex Address: x’EE Bit 2 Bit 1 Bit ...
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... Channel Command register Channel number 0 0 Channel Channel Channel Channel 3 Bit 4 Bit chmd2 chmd1 chmd0 Intel Hex Address: x’18 Motorola Hex Address: x’1B Bit 2 Bit 1 Bit 0 chmd2 chmd1 chmd0 Mode HDLC Reserved Async Reserved Async–HDLC/PPP SLIP MNP 4/ARAP Reserved Datasheet ...
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... Advanced Multi-Protocol Communications Controller — CD2431 Bit 4 Bit 3 AdMd0 Flag3 1 byte 2 byte Flag 2 Flag 1 Flag through Intel Hex Address: x’13 Motorola Hex Address: x’10 Bit 2 Bit 1 Bit 0 Flag2 Flag1 Flag0 minimum of one opening flag, with shared closing/opening flags permitted minimum number of opening flags sent 91 ...
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... Chl3 Chl2 Chl1 Chl0 Intel Hex Address: x’13 Motorola Hex Address: x’10 Bit 2 Bit 1 Bit 0 Chl2 Chl1 Chl0 Partly Character Length 0 5 bits 1 6 bits 0 7 bits 1 8 bits Datasheet ...
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... Advanced Multi-Protocol Communications Controller — CD2431 Bit 4 Bit 3 CRCNinv 0 Bit 4 Bit 3 0 RLM Intel Hex Address: x’14 Motorola Hex Address: x’17 Bit 2 Bit 1 Bit 0 RtsAO CtsAE DsrAE Intel Hex Address: x’14 Motorola Hex Address: x’17 Bit 2 Bit 1 Bit 0 RtsAO CtsAE DsrAE 93 ...
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CD2431 — Advanced Multi-Protocol Communications Controller Bit 7 Implied XON mode IXM has meaning only if TxIBE is set. If transmission stops due to a received XOFF character, and: If IXM = 0, transmission resumes only after the receipt of ...
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... DSR* is asserted low, the receiver input is enabled for the next character. If DSR* is high, the receiver is disabled until DSR* goes low. Datasheet Advanced Multi-Protocol Communications Controller — CD2431 Bit 4 Bit 3 0 RLM Intel Hex Address: x’14 Motorola Hex Address: x’17 Bit 2 Bit 1 Bit 0 RtsAO CtsAE DsrAE ...
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... The number of character times preceding any frame transmission. A character time is 10 bit times. All zeros in this field disables the leading pads. 96 Bit 4 Bit 3 TxGen npad3 npad3 npad2 npad1 npad0 Intel Hex Address: x’15 Motorola Hex Address: x’16 Bit 2 Bit 1 Bit 0 npad2 npad1 npad0 Number of leading pads Datasheet ...
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... All zeros in this field disables the leading pads. Datasheet Advanced Multi-Protocol Communications Controller — CD2431 Bit 4 Bit 3 TxGen npad3 npad3 npad2 npad1 Intel Hex Address: x’15 Motorola Hex Address: x’16 Bit 2 Bit 1 Bit 0 npad2 npad1 npad0 npad0 Number of leading pads ...
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... These bits specify the number of synchronous characters sent. 101–111 are reserved. 98 Bit 4 Bit 3 FCS idle npad2 npad1 npad0 Intel Hex Address: x’15 Motorola Hex Address: x’16 Bit 2 Bit 1 Bit 0 npad2 npad1 npad0 Reserved 1 pad character sent 2 pad characters sent 3 pad characters sent 4 pad characters sent Datasheet ...
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... Bit 3 0 npad3 npad2 npad1 npad0 Bit 4 Bit 3 SCDE Splstp Intel Hex Address: x’15 Motorola Hex Address: x’16 Bit 2 Bit 1 Bit 0 npad2 npad1 npad0 Number of leading pads Intel Hex Address: x’15 Motorola Hex Address: x’16 Bit 2 Bit 1 Bit 0 Stop2 Stop1 Stop0 99 ...
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... Detect one-to-zero transition on the CD* input (zero-to-one transition of CD (MSVR) bit) 100 Stop2 Stop1 Stop0 stop bit 1.5 stop bits stop bits Bit 4 Bit 3 0 Stop Bit Length Intel Hex Address: x’16 Motorola Hex Address: x’15 Bit 2 Bit 1 Bit 0 FIFO threshod Datasheet ...
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... This bit is ignored when bits 3:0 are all zeros Use out-of-band flow control (DTR pin Use in-band flow control (automatic transmission of XOFF/XON characters) Datasheet Advanced Multi-Protocol Communications Controller — CD2431 Bit 4 Bit 3 In/Out Intel Hex Address: x’17 Motorola Hex Address: x’14 Bit 2 Bit 1 Bit 0 Rx flow control threshold 101 ...
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... CD2431 Action DTR asserted DTR deasserted XON transmitted XOFF transmitted Intel Hex Address: x’1B Motorola Hex Address: x’18 Bit 2 Bit 1 Bit 0 ParMrk INPCK ParInt No special action on CR and NL NL translated translated translated to NL and NL translated discarded CR discarded and NL translated discarded CR discarded and NL translated to CR ...
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... Ignore error; character passed on as good data Discard error character Reserved Translate to a sequence of FF NULL and the error character and pass on as Good Data Reserved Reserved Intel Hex Address: x’04 Motorola Hex Address: x’07 Bit 2 Bit 1 Bit 0 0 ONLCR OCRNL ...
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... ONLCR OCRNL special action translated to NL translated to the sequence CR NL. CR translated to NL and NL translated to the 1 1 sequence CR NL. Bit 4 Bit 3 User-defined Special Character, protcol-defined Special Characters (see below). Intel Hex Address: x’1C Motorola Hex Address: x’1F Bit 2 Bit 1 Bit 0 Datasheet ...
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... Advanced Multi-Protocol Communications Controller — CD2431 Bit 4 Bit 3 User-defined Special Character, protcol-defined Special Characters (see below). Bit 4 Bit 3 User-defined special character Intel Hex Address: x’1D Motorola Hex Address: x’1E Bit 2 Bit 1 Bit 0 Intel Hex Address: x’1E Motorola Hex Address: x’1D Bit 2 Bit 1 Bit 0 105 ...
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... Bit 3 User-defined special character detect range, high Intel Hex Address: x’1F Motorola Hex Address: x’1C Bit 2 Bit 1 Bit 0 Intel Hex Address: x’20 Motorola Hex Address: x’23 Bit 2 Bit 1 Bit 0 Intel Hex Address: x’21 Motorola Hex Address: x’22 Bit 2 Bit 1 Bit 0 Datasheet ...
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... Frame Qualification Address 1 Bit 4 Bit 3 Frame Qualification Address 2 Intel Hex Address: x’2D Motorola Hex Address: x’2E Bit 2 Bit 1 Bit 0 Intel Hex Address: x’1C Motorola Hex Address: x’1F Bit 2 Bit 1 Bit 0 Intel Hex Address: x’1D Motorola Hex Address: x’1E Bit 2 Bit 1 Bit 0 107 ...
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... Frame Qualification Address 4 Bit 4 Bit Intel Hex Address: x’1E Motorola Hex Address: x’1D Bit 2 Bit 1 Bit 0 Intel Hex Address: x’1F Motorola Hex Address: x’1C Bit 2 Bit 1 Bit 0 page 91. Intel Hex Address: x’D4 Motorola Hex Address: x’D6 Bit 2 Bit 1 Bit Poly Datasheet ...
Page 109
... User-defined mapped transmit character Bit 4 Bit 3 User-defined mapped transmit character Intel Hex Address: x’1B Motorola Hex Address: x’18 Bit 2 Bit 1 Bit 0 Intel Hex Address: x’04 Motorola Hex Address: x’07 Bit 2 Bit 1 Bit 0 Intel Hex Address: x’2D Motorola Hex Address: x’2E Bit 2 Bit 1 Bit 0 109 ...
Page 110
... Bit 1 Bit 0 Char. 01 Char. 00 Intel Hex Address: x’1D Motorola Hex Address: x’1E Bit 1 Bit 0 Char. 09 Char. 08 Intel Hex Address: x’1E Motorola Hex Address: x’1D Bit 1 Bit 0 Char. 11 Char. 10 Intel Hex Address: x’1F Motorola Hex Address: x’1C Bit 1 Bit 0 Char. 19 Char. 18 Datasheet ...
Page 111
... Intel Hex Address: x’20 Motorola Hex Address: x’23 Bit 2 Bit 1 Bit 0 Char. 02 Char. 01 Char. 00 Intel Hex Address: x’21 Motorola Hex Address: x’22 Bit 2 Bit 1 Bit 0 Char. 0A Char. 09 Char. 08 Intel Hex Address: x’22 Motorola Hex Address: x’21 Bit 2 Bit 1 Bit 0 Char. 12 Char. 11 Char. 10 111 ...
Page 112
... RBPR. 112 Bit 4 Bit 3 Bit 2 Char. 1C Char. 1B Char. 1A Bit 4 Bit 3 Bit 2 Receive Bit Rate Period (Divisor) Intel Hex Address: x’23 Motorola Hex Address: x’20 Bit 1 Bit 0 Char. 19 Char. 18 Intel Hex Address: x’C9 Motorola Hex Address: x’CB Bit 1 Bit 0 Datasheet ...
Page 113
... Dpllmd0 Dpllmd0 Encoding 0 0 NRZ 0 1 NRZI 1 0 Manchester 1 1 Reserved Clksel1 Clksel0 Clk Clk Clk Clk Clk Reserved External clock Reserved Section 5.5. Intel Hex Address: x’CA Motorola Hex Address: x’C8 Bit 2 Bit 1 Bit 0 ClkSel2 ClkSel1 ClkSel0 Clock Source 113 ...
Page 114
... ClkSel2 ClkSel1 ClkSel0 Section 5.5. Intel Hex Address: x’C1 Motorola Hex Address: x’C3 Bit 2 Bit 1 Bit 0 Intel Hex Address: x’C2 Motorola Hex Address: x’C0 Bit 2 Bit 1 Bit 0 0 LLM 0 Select Clk 0 Clk 1 Clk 2 Clk 3 Clk 4 Reserved External clock Receive clock Datasheet ...
Page 115
... The user must take care when waiting for command completions at critical times, that is, during interrupt service routines. Datasheet Advanced Multi-Protocol Communications Controller — CD2431 Bit 4 Bit 3 RstAll EnTx Intel Hex Address: x’10 Motorola Hex Address: x’13 Bit 2 Bit 1 Bit 0 DisTx EnRx DisRx ...
Page 116
CD2431 — Advanced Multi-Protocol Communications Controller Channel Control Commands (Bit Bit 7 Must be ‘0’. Bit 6 Clear Channel Command When this command is issued, the CD2431 clears the data FIFOs and current trans- mit and receive ...
Page 117
... DMA buffers have to be returned to the CD2431 before transmit transfers begin again. Bits 2:0 Reserved – must be ‘0’. Datasheet Advanced Multi-Protocol Communications Controller — CD2431 Bit 4 Bit 3 ClrRcv ClrTx Intel Hex Address: x’10 Motorola Hex Address: x’13 Bit 2 Bit 1 Bit 117 ...
Page 118
... COR5. Bit 0 Send XOFF Causes the transmission of an XOFF (cntl-S or hex 13). The command structure associated with the sndsp Control bit is: 118 Bit 4 Bit SndSpc Intel Hex Address: x’11 Motorola Hex Address: x’12 Bit 2 Bit 1 Bit 0 Frame Xon Xoff Datasheet ...
Page 119
... Datasheet Advanced Multi-Protocol Communications Controller — CD2431 frame Xon Bit 4 Bit 3 0 SndSpc Xoff Action X Send Special Disabled X Send one character with FE X Send Xon 1 Send Ooff Intel Hex Address: x’11 Motorola Hex Address: x’12 Bit 2 Bit 1 Bit 0 Frame 0 0 119 ...
Page 120
... RxEn and the TxEn bits are controlled by host CPU commands to the CCR. 120 Bit 4 Bit 3 0 SndSpc SSPC2 SSCP1 SSPC0 Intel Hex Address: x’11 Motorola Hex Address: x’12 Bit 2 Bit 1 Bit 0 SSPC2 SSPC1 SSPC0 Function Reserved Send Special Character 1 Send Special Character 2 Send Special Character 3 Send Special Character 4 Reserved Reserved Reserved Datasheet ...
Page 121
... Currently transmitting frame. Bit 0 Tx Mark 0 = Currently not transmitting continuous ones Currently transmitting continuous ones. Datasheet Advanced Multi-Protocol Communications Controller — CD2431 Bit 4 Bit 3 RxMark TxEn Intel Hex Address: x’19 Motorola Hex Address: x’1A Bit 2 Bit 1 Bit 0 TxFlag TxFrame TxMark 121 ...
Page 122
... Bit 0 Reserved — always returns ‘0’ when read. 122 Bit 4 Bit 3 Bit 2 0 TxEn TxFloff Intel Hex Address: x’19 Motorola Hex Address: x’1A Bit 1 Bit 0 TxFlon 0 Datasheet ...
Page 123
... When clear, the transmitter output is not idle. Note that TFram and TIdle are mutually exclusive. Datasheet Advanced Multi-Protocol Communications Controller — CD2431 Bit 4 Bit 3 Ridle TxEn Intel Hex Address: x’19 Motorola Hex Address: x’1A Bit 2 Bit 1 Bit 0 TxFloff TFram Tidle 123 ...
Page 124
... Transmitter Idle Status When set, the transmitter output is idle. When clear, the transmitter output is not idle. Note that TFram and TIdle are mutually exclusive. 124 Bit 4 Bit 3 Bit 2 Ridle TxEn 0 Intel Hex Address: x’19 Motorola Hex Address: x’1A Bit 1 Bit 0 TFram Tidle Datasheet ...
Page 125
... Advanced Multi-Protocol Communications Controller — CD2431 Bit 4 Bit 3 DTRop 0 Bit 4 Bit 3 DTRop 0 Intel Hex Address: x’DC Motorola Hex Address: x’DE Bit 2 Bit 1 Bit 0 0 DTR RTS Intel Hex Address: x’DD Motorola Hex Address: x’DF Bit 2 Bit 1 Bit 0 0 DTR RTS 125 ...
Page 126
... X X IT[1:0] Group/Type Group 1 — modem signal change interrupt/general 01 timer interrupt. 10 Group 2 — transmit data interrupt. 11 Group 3 — receive data interrupt. 00 Group 3 — eceive exception interrupt. Intel Hex Address: x’0A Motorola Hex Address: x’09 Bit 2 Bit 1 Bit 0 X ‘IT1 IT0 Datasheet ...
Page 127
... Group 2 interrupts are generated at the end of transmit DMA buffers or when the FIFO threshold is reached in Interrupt Transfer mode. Datasheet Advanced Multi-Protocol Communications Controller — CD2431 Bit 4 Bit 3 0 RxD Intel Hex Address: x’12 Motorola Hex Address: x’11 Bit 2 Bit 1 Bit 0 TIMER TxMpty TxD ...
Page 128
... These per-channel registers are initialized with each channel number. The locations are RAM registers and can be used for any purpose. 128 Bit 4 Bit RxD Bit 4 Bit Intel Hex Address: x’12 Motorola Hex Address: x’11 Bit 2 Bit 1 Bit 0 TIMER TxMpty TxD Intel Hex Address: x’25 Motorola Hex Address: x’26 Bit 2 Bit 1 Bit Datasheet ...
Page 129
... Currently in a modem interrupt service, MIR provides the current channel number Currently in a transmit interrupt service, TIR provides the current channel number Currently in a receive interrupt service, RIR provides the current channel number. Intel Hex Address: x’E0 Motorola Hex Address: x’E2 Bit 2 Bit 1 Bit 0 TLvl [0] MLvl [0] CLvl [0] 129 ...
Page 130
... Bit 4 Bit 3 Bit 2 User-assigned priority match value Bit 4 Bit 3 Bit 2 0 Rvct [1] Rvct [0] Intel Hex Address: x’E3 Motorola Hex Address: x’E1 Bit 1 Bit 0 Intel Hex Address: x’EF Motorola Hex Address: x’ED Bit 1 Bit 0 Rcn [1] Rcn [0] Datasheet ...
Page 131
... Receive interrupt requested, but not asserted Receive interrupt asserted Receive interrupt acknowledged Receive interrupt service routine completed. Bit 12 Bit 11 RISR High Bit 4 Bit 3 RISR Low Sequence of Events Intel Hex Address: x’8A Motorola Hex Address: x’88 Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 131 ...
Page 132
... During an interrupt service routine, the host can use this register to provide a timer value as detailed in the Receive End of Interrupt register. The host can only load one of the two timers in the interrupt service routine. 132 Bit 4 Bit 3 Bit 2 CRC OE Reslnd Intel Hex Address: x’8A Motorola Hex Address: x’89 Bit 1 Bit 0 0 ClrDct Datasheet ...
Page 133
... COR3) Special Character 4 matched (only if ESCDE is enabled 100 in COR3) Character is within the inclusive range of the characters 111 in the Special Character Range low and high registers (only if RngDE is enabled in COR3). Intel Hex Address: x’8A Motorola Hex Address: x’89 Bit 2 Bit 1 Bit Break ...
Page 134
... The table below defines the encoding of RxABT and FE for an aborted receive frame: 134 Bit 4 Bit 3 Bit 2 CRC OE FE Intel Hex Address: x’8A Motorola Hex Address: x’89 Bit 1 Bit 0 0 Break Datasheet ...
Page 135
... Datasheet Advanced Multi-Protocol Communications Controller — CD2431 Error None Not used Received aboft sequence: x’7D, x”7E Framing error caused a frame abort Bit 4 Bit Intel Hex Address: x’8A Motorola Hex Address: x’89 Bit 2 Bit 1 Bit Break 135 ...
Page 136
... Reserved – always returns ‘0’ when read. 136 Bit 4 Bit 3 0 BA/BB Bit 4 Bit 3 0 RxCt4 RxCt3 Intel Hex Address: x’8B Motorola Hex Address: x’88 Bit 2 Bit 1 Bit Intel Hex Address: x’33 Motorola Hex Address: x’30 Bit 2 Bit 1 Bit 0 RxCt2 RxCt1 RxCt0 Datasheet ...
Page 137
... Datasheet Advanced Multi-Protocol Communications Controller — CD2431 Bit 4 Bit Bit 4 Bit 3 SetTm1 NoTrans Intel Hex Address: x’F8 Motorola Hex Address: x’F8 Bit 2 Bit 1 Bit Intel Hex Address: x’87 Motorola Hex Address: x’84 Bit 2 Bit 1 Bit 0 Gap2 Gap1 Gap0 137 ...
Page 138
... Bit 6 Discard Exception Character (DMA mode only) When this bit is set in response to an async exception interrupt, the exception char- acter is not transferred to memory. 138 Bit 4 Bit 3 Bit 2 SetTm1 NoTrans 0 Intel Hex Address: x’87 Motorola Hex Address: x’84 Bit 1 Bit Datasheet ...
Page 139
... Datasheet Advanced Multi-Protocol Communications Controller — CD2431 Bit 4 Bit 3 User-assigned priority match value Intel Hex Address: x’E2 Motorola Hex Address: x’E0 Bit 2 Bit 1 Bit 0 139 ...
Page 140
... Bit 3 0 Tvct [1] Ten Tact Teoi Intel Hex Address: x’EE Motorola Hex Address: x’EC Bit 2 Bit 1 Bit 0 Tvct [0] Tcn [1] Tcn [0] Sequence of Events Idle Transmit interrupt requested, but not asserted Transmit interrupt asserted Transmit interrupt acknowledged Transmit interrupt service routine completed Datasheet ...
Page 141
... Advanced Multi-Protocol Communications Controller — CD2431 Bit 4 Bit 3 UE BA/BB Bit 4 Bit 3 TxCt4 TxCt3 Intel Hex Address: x’89 Motorola Hex Address: x’8A Bit 2 Bit 1 Bit 0 0 TxEmpty TxDat Intel Hex Address: x’83 Motorola Hex Address: x’80 Bit 2 Bit 1 Bit 0 TxCt2 TxCt1 TxCt0 141 ...
Page 142
... Bit 4 Bit 3 Bit Bit 4 Bit 3 Bit 2 SetTm1 Notrans 0 Intel Hex Address: x’F8 Motorola Hex Address: x’F8 Bit 1 Bit Intel Hex Address: x’86 Motorola Hex Address: x’85 Bit 1 Bit Datasheet ...
Page 143
... Datasheet Advanced Multi-Protocol Communications Controller — CD2431 Bit 4 Bit 3 User-assigned priority match value Intel Hex Address: x’E1 Motorola Hex Address: x’E3 Bit 2 Bit 1 Bit 0 143 ...
Page 144
... Bit 3 0 Mvct [1] Mer Mact Meo Intel Hex Address: x’ED Motorola Hex Address: x’EF Bit 2 Bit 1 Bit 0 Mvct [0] Mcn [1] Mcn [0] Sequence of Events Idle Modem interrupt requested, but not asserted Modem interrupt asserted Modem interrupt acknowledged Modem interrupt service routine completed Datasheet ...
Page 145
... Reserved – always returns ‘0’ when read. Datasheet Advanced Multi-Protocol Communications Controller — CD2431 Bit 4 Bit Bit 4 Bit 3 SetTm1 0 Intel Hex Address: x’88 Motorola Hex Address: x’8B Bit 2 Bit 1 Bit 0 0 Timer2 Timer1 Intel Hex Address: x’85 Motorola Hex Address: x’86 Bit 2 Bit 1 Bit 145 ...
Page 146
... The CD2431 always performs 8-bit DMA transfers, the position of the data on the bus still follows the normal rules relating to the BYTESWAP pin. Bits 2:0 Reserved – always returns ‘0’ when read. 146 Bit 4 Bit ByteDMA Intel Hex Address: x’F4 Motorola Hex Address: x’F6 Bit 2 Bit 1 Bit Datasheet ...
Page 147
... Datasheet Advanced Multi-Protocol Communications Controller — CD2431 Bit 4 Bit 3 Binary value Bit 4 Bit 3 Append Ntbuf Intel Hex Address: x’8D Motorola Hex Address: x’8E Bit 2 Bit 1 Bit 0 Intel Hex Address: x’1A Motorola Hex Address: x’19 Bit 2 Bit 1 Bit 0 Tbusy Nrbuf Rbusy 147 ...
Page 148
... Access: Word Read/Write Bit 15 Bit 14 Bit 13 Bit 7 Bit 6 Bit 5 148 Bit 12 Bit 11 Binary address value, 32-bit address, bits 15:8 Bit 4 Bit 3 Binary address value, 32-bit address, bits 7:0 Intel Hex Address: x’40 Motorola Hex Address: x’42 Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 Datasheet ...
Page 149
... Intel Hex Address: x’42 Motorola Hex Address: x’40 Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 Intel Hex Address: x’44 Motorola Hex Address: x’46 Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 Intel Hex Address: x’46 Motorola Hex Address: x’44 Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 149 ...
Page 150
... Binary count value, 16-bit count, bits 15:8 Bit 4 Bit 3 Binary count value, 16-bit count, bits 7:0 Intel Hex Address: x’48 Motorola Hex Address: x’4A Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 Intel Hex Address: x’4A Motorola Hex Address: x’48 Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 Datasheet ...
Page 151
... Datasheet Advanced Multi-Protocol Communications Controller — CD2431 Bit 4 Bit Bit 4 Bit Intel Hex Address: x’4C Motorola Hex Address: x’4F Bit 2 Bit 1 Bit 2431own Intel Hex Address: x’4D Motorola Hex Address: x’4E Bit 2 Bit 1 Bit 2431own 151 ...
Page 152
... Binary address value, 32-bit address, bits 23:16 Section 8.5.2.7 on page 137 for the insertion of status information by the host. Intel Hex Address: x’3C Motorola Hex Address: x’3E Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 Intel Hex Address: x’3E Motorola Hex Address: x’3C Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 Datasheet ...
Page 153
... Intel Hex Address: x’50 Motorola Hex Address: x’52 Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 Intel Hex Address: x’52 Motorola Hex Address: x’50 Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 Intel Hex Address: x’54 Motorola Hex Address: x’56 Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 153 ...
Page 154
... Binary count value, 16-bit count, bits 15:8 Bit 4 Bit 3 Binary count value, 16-bit count, bits 7:0 Intel Hex Address: x’56 Motorola Hex Address: x’54 Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 Intel Hex Address: x’58 Motorola Hex Address: x’5A Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 Datasheet ...
Page 155
... Intel Hex Address: x’5A Motorola Hex Address: x’58 Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 Intel Hex Address: x’5C Motorola Hex Address: x’5F Bit 2 Bit 1 Bit 0 map32 INTR 2431own Intel Hex Address: x’5D Motorola Hex Address: x’5E Bit 2 Bit 1 Bit 0 map32 INTR 2431own 155 ...
Page 156
... Access: Byte Read/Write Bit 7 Bit 6 Bit 5 Berr EOF EOB 156 Bit 4 Bit 3 Bit Bit 4 Bit 3 Bit Intel Hex Address: x’5C Motorola Hex Address: x’5F Bit 1 Bit 0 INTR 2431own Intel Hex Address: x’5D Motorola Hex Address: x’5E Bit 1 Bit 0 INTR 2431own Datasheet ...
Page 157
... CD2431. Status bits within the register are defined as: Datasheet Advanced Multi-Protocol Communications Controller — CD2431 Bit 4 Bit Bit 4 Bit Intel Hex Address: x’5C Motorola Hex Address: x’5F Bit 2 Bit 1 Bit 0 0 INTR 2431own Intel Hex Address: x’5D Motorola Hex Address: x’5E Bit 2 Bit 1 Bit 0 0 INTR 2431own 157 ...
Page 158
... Access: Byte Read/Write Bit 7 Bit 6 Bit 5 Berr EOF EOB 158 Bit 4 Bit 3 Bit 2 0 Append 0 Bit 4 Bit 3 Bit Intel Hex Address: x’5C Motorola Hex Address: x’5F Bit 1 Bit 0 INTR 2431own Intel Hex Address: x’5D Motorola Hex Address: x’5E Bit 1 Bit 0 INTR 2431own Datasheet ...
Page 159
... Bit 5 Datasheet Advanced Multi-Protocol Communications Controller — CD2431 Bit 12 Bit 11 Binary address value, 32-bit address, bits 15:8 Bit 4 Bit 3 Binary address value, 32-bit address, bits 7:0 Intel Hex Address: x’38 Motorola Hex Address: x’3A Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 159 ...
Page 160
... Binary address value, 32-bit address, bits 31:24 Bit 4 Bit 3 Binary address value, 32-bit address, bits 23:16 Bit 4 Bit 3 Binary value Intel Hex Address: x’3A Motorola Hex Address: x’38 Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 Intel Hex Address: x’D8 Motorola Hex Address: x’DA Bit 2 Bit 1 Bit 0 Datasheet ...
Page 161
... Bit 4 Bit 3 Binary value Intel Hex Address: x’26 Motorola Hex Address: x’24 Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 Intel Hex Address: x’26 Motorola Hex Address: x’25 Bit 2 Bit 1 Bit 0 Intel Hex Address: x’27 Motorola Hex Address: x’24 Bit 2 Bit 1 Bit 0 161 ...
Page 162
... Bit 2 Binary value Bit 4 Bit 3 Bit 2 Binary value Intel Hex Address: x’28 Motorola Hex Address: x’2A Bit 9 Bit 8 Bit 1 Bit 0 Intel Hex Address: x’28 Motorola Hex Address: x’2B Bit 1 Bit 0 Intel Hex Address: x’29 Motorola Hex Address: x’2A Bit 1 Bit 0 Datasheet ...
Page 163
... Datasheet Advanced Multi-Protocol Communications Controller — CD2431 Bit 4 Bit 3 Binary value Bit 4 Bit 3 Binary value Intel Hex Address: x’2A Motorola Hex Address: x’29 Bit 2 Bit 1 Bit 0 Intel Hex Address: x’2A Motorola Hex Address: x’29 Bit 2 Bit 1 Bit 0 163 ...
Page 164
CD2431 — Advanced Multi-Protocol Communications Controller 9.0 Electrical Specifications Note: Verify with your local sales office that you have the latest datasheet before finalizing a design. 9.1 Absolute Maximum Ratings Operating ambient temperature (T Storage temperature 150 ...
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AC Electrical Characteristics Symbol t Period of CLK input (35 MHz maximum) PERIOD t CLK high to BUSCLK high 1 t CLK high to BUSCLK low 2 Bus Arbitration t CLK high to BGACK* tristate 11 t BGIN* low ...
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CD2431 — Advanced Multi-Protocol Communications Controller Symbol t R/W* setup to CLK high 44 t CLK high to data valid 45 t Data setup time to CLK high 46 t Data hold time after CLK high 47 t Address setup ...
Page 167
Figure 22. Slave Read Cycle Timing CLK BUSCLK t 41 DS A[0–7] A/D[0–15] DTACK DATEN* /DATDIR* Datasheet Advanced Multi-Protocol Communications Controller — CD2431 ...
Page 168
CD2431 — Advanced Multi-Protocol Communications Controller Figure 23. Slave Write Cycle Timing CLK BUSCLK t 41 DS A[0–7] A/D[0–15] DTACK DATEN* 168 ...
Page 169
Figure 24. Interrupt Acknowledge Cycle Timing CLK BUSCLK t 61 DS A[0–7] A/D[0–15] DTACK DATEN* /DATDIR* Datasheet Advanced Multi-Protocol Communications Controller — CD2431 ...
Page 170
CD2431 — Advanced Multi-Protocol Communications Controller Figure 25. Bus Arbitration Cycle Timing CLK BUSCLK BR* BGIN* ADLD* A[0–7] A/D[0–15] AS* AEN*/DATEN*/ DATDIR* BGACK* R/W* NOTE: In DMA Read cycle, these pins will be tristate; in DMA Write cycle, these pins ...
Page 171
Figure 26. Bus Release Timing CLK BUSCLK AS*, DS* A[0–7] A/D[0–15] BGACK* R/W* DATEN*, AEN*, DATDIR* Datasheet Advanced Multi-Protocol Communications Controller — CD2431 171 ...
Page 172
CD2431 — Advanced Multi-Protocol Communications Controller Figure 27. DMA Read Cycle Timing CLK BUSCLK A[0–7] A/D[0–15] DTACK* BERR* 172 BERR* Timing: ...
Page 173
Figure 28. DMA Write Cycle Timing CLK BUSCLK t 24 AS* DS A[0– A/D[0–15] DTACK* BERR* Datasheet Advanced Multi-Protocol Communications Controller — CD2431 BERR* Timing setup ...
Page 174
... MAX NOTES: 1. Dimensions are in millimeters (inches), and controlling dimension is millimeter. 2. Before beginning any new design with this device, please contact Intel for the latest package information. 174 22.95 (0.904) 23.45 (0.923) 19.90 (0.783) 20.10 (0.791) ...
Page 175
... Ordering Information Product line: Communications, Data Part number Internal reference number † Contact Intel Corporation for up-to-date information on revisions. Datasheet Advanced Multi-Protocol Communications Controller — CD2431 SCD243110QCD Temperature range Commercial Package type: MQFP Metric quad flat pack † Revision 175 ...
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...
Page 177
Index Numerics 32-bit data bus and C fields 69 abbreviations 13 absolute maximum ratings 164 AC electrical characteristics bus arbitration 165 DMA read 165 DMA write 165 host read/write 165 interrupt acknowledge 166 ACCM (async-control-character map) 70 ...
Page 178
FCS (frame check sequence) 67 FCS mode 98 FCT (flow control transparency) mode 100, 106 fields, A and C 69 FIFO and timer operations 41 Flag Hunt mode 68 Flag mode 67, 68 format character 69 frame 69 frame format ...
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HDLC mode 91, 93, 98, 132 High-Impedance mode 18 Idle mode 98 Idle-in Flag mode 98 Idle-in Mark mode 98 Local Loopback mode 114 Mark mode 67, 68 MNP4 mode 97 MNP4/SLIP mode 95 Parity mode 92 Protocol mode 90 ...
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BERCNT 23, 31, 147 DMABSTS 23, 31, 147 DMR 23, 31, 146 DMA Transmit registers ATBADRL 24, 32, 153 ATBADRU 24, 32, 153 ATBCNT 24, 32, 154 ATBSTS 24, 32, 155, 156, 157, 158 BTBADRL 24, 32, 153 BTBADRU 24, ...
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S service routine receive DMA interrupt 87 transmit interrupt 88 setup examples async interrupt 86 HDLC DMA channel 86 SLIP mode 99, 135 SLIP/MNP4 mode 119, 124 Syn/Flag Hunt mode 117 Synchronous mode 98 synchronous transmitter examples 48 T timers ...
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...
Page 183
Bit Index Numerics 2431own 151, 155–158 A AbortTx 118–120 AdMd[1:0] 91 AFLO 91 Alt1 98 AppdCmp 120 Append 147 B BA/BB 136, 141 Berr 136, 141, 151, 155–158 Break 133–135 ByteDMA 146 C C[1:0] 89, 128 CD 125 CDChg 145 ...
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FCT 99 FE 133–135 FIFO threshod 100 Flag[3:0] 91 Frame 118–119 Frame Qualification Address [4:0] 107 G Gap[2:0] 137 I ICRNL 102 idle 98 IgnBrk 102 IgnCR 102 Ignore 92 In/Out 101 InitCh 115 INLCF 102 INPCK 102 INTR 155–158 ...
Page 185
RxAbt 132, 134–135 RxChk 96–97 RxCt[4:0] 136 RxD 127–128 RxEn 121–124 RxFlag 121 RxFloff 122–123 RxFlon 122 RxFrame 121 RxMark 121 RxMode 90 S SCDE 99 SCdet[2:0] 133 SetTm[1:0] 137–138, 142, 145 sndpad 98 SndSpc 118–120 Splstp 99 SSPC[2:0] 120 ...
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