1893Y-10 IDT, Integrated Device Technology Inc, 1893Y-10 Datasheet - Page 29

• Manufacturer Part Number: 1893Y-10
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 1893Y-10

• Lead Free Status / RoHS Status: Not Compliant

6.3 10M Serial Interface
ICS1893 Rev C 6/6/00
When the Mac/Repeater Interface is configured as a 10M Serial Interface, the ICS1893 and the
MAC/repeater exchange a framed, serial bit stream along with associated control signals. The 10M Serial
Interface configuration is ideally suited to applications that already incorporate a serial 10Base-T MAC with
a standard ‘ 7-wire’ interface. The ICS1893 MAC/Repeater Interface can be configured for 10M Serial
Interface operations, as determined by ICS1893 configuration functions. When the HW/SW pin is set for:
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A10M Serial Interface has two data paths: one for data transmission and one for data reception. Each data
path exchanges a serial bit stream with the MAC/repeater at a 10-MHz clock rate. A benefit of using the
10M Serial Interface – in contrast to the 10M MII Interface – is a reduction in the bit latency through the
ICS1893. This reduction is attributed to eliminating both parallel-to-serial and serial-to-parallel data
conversions.
The 10M Serial Interface consists of the following eight signals:
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When the ICS1893’ s MAC/Repeater Interface is configured for 10M Serial operations, both its default MII
pin names and their associated functions are redefined. For more information, see
“ MAC/Repeater Interface Pins for 10M Serial Interface”
Note:
Hardware mode, the 10M Serial Interface is selected when both of the following are true:
Software mode, the 10M Serial Interface is selected when both of the following are true:
10COL
10CRS
10RCLK
10RD
10RXDV
10TCLK
10TD
10TXEN
– The MII/SI input pin is logic one (that is, the selection is for a Serial Interface).
– The 10/100SEL input pin is logic zero (that is, the selection is for 10M operations).
– The MII/SI input pin is logic one (that is, the selection is for a Serial Interface).
– The Control Register Data Rate bit (bit 0.13) is logic zero (that is, the selection is for 10M operations).
ICS1893 - Release
In software mode, the 10/100SEL pin becomes an output that indicates the state of bit 0.13.
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
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Chapter 6 Interface Overviews
Section 9.3.4.3,
June, 2000