PIC16LF1517-E/PT Microchip Technology, PIC16LF1517-E/PT Datasheet - Page 84

• Manufacturer Part Number: PIC16LF1517-E/PT
• Description: 40-pin, 14KB Flash, 512B RAM, 10-bit ADC, 2xCCP, SPI, MI2C, EUSART, 1.8V-3.6V 44
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1517-E/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 28x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: *
• Processor Series: PIC16LF151x
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC16(L)F1516/7/8/9
7.6.5
The PIR2 register contains the interrupt flag bits, as
shown in
REGISTER 7-5:
DS41452A-page 84
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6-4
bit 3
bit 2-1
bit 0
R/W-0/0
OSFIF
Register
PIR2 REGISTER
OSFIF: Oscillator Fail Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
Unimplemented: Read as ‘0’
BCLIF: MSSP Bus Collision Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
Unimplemented: Read as ‘0’
CCP2IF: CCP2 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
7-5.
U-0
—
PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U-0
—
U-0
Preliminary
—
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
R/W-0/0
BCLIF
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
U-0
—
software
 2010 Microchip Technology Inc.
should
U-0
—
ensure
R/W-0/0
CCP2IF
bit 0
the