PIC16LF1847-E/ML Microchip Technology, PIC16LF1847-E/ML Datasheet
PIC16LF1847-E/ML
Specifications of PIC16LF1847-E/ML
Related parts for PIC16LF1847-E/ML
PIC16LF1847-E/ML Summary of contents
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... Flash Microcontrollers 2011 Microchip Technology Inc. PIC16(L)F1847 with nanoWatt XLP Technology Preliminary Data Sheet DS41453B ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Programmable clock output frequency and duty-cycle Special Microcontroller Features: • 1.8V-5.5V Operation – PIC16F1847 • 1.8V-3.6V Operation – PIC16LF1847 • Self-Programmable under Software Control • Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) • Programmable Brown-out Reset (BOR) • ...
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... Sensing Oscillator module input channels • Data Signal Modulator module: - Selectable modulator and carrier sources • SR Latch: - Multiple Set/Reset input options - Emulates 555 Timer applications PIC16(L)F1847 Family Types Program Data Memory Memory PIC16LF1847 8K 1024 PIC16F1847 8K 1024 One pin is input only. Note 1: DS41453B-page 4 256 16 ...
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Pin Diagram – 18-Pin PDIP, SOIC PIC16(L)F1847) ( PDIP, SOIC RA2/AN2/C12IN2-/C12IN+/V RA3/AN3/C12IN3-/C1IN+/V RA4/AN4/C2OUT/T0CKI/CCP4/SRNQ RB0/T1G/CCP1 RB1/AN11/RX (1,2) (1,2) (1) RB2/AN10/MDMIN/TX /CK /RX /DT RB3/AN9/MDOUT/CCP1 Note 1: Pin function is remappable via APFCON register. 2: Default function location. Pin Diagram – 20-Pin ...
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... RA5/ MCLR/V /SS1 (1) (1) RB0/T1G/CCP1 /P1A /INT/SRI/FLT0 Note 1: Pin function is remappable via APFCON register. DS41453B-page 6 PIC16(L)F1847 RA7/OSC1/CLKIN/P1C 20 RA6/OSC2/CLKOUT/CLKR/P1D PIC16(L)F1847 RB7/AN6/T1OSCO/P1D 15 RB6/AN5/T1CKI/T1OSCI/P1C Preliminary (1) (1) (1) /CCP2 /P2A (1) (1) (1) /P2B /SDO1 (1) (1) /P2B /MDCIN1/ICSPDAT (1) (1) (1) /CCP2 /P2A /ICSPCLK 2011 Microchip Technology Inc. ...
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TABLE 1: 18/20/28-PIN SUMMARY (PIC16(L)F1847) RA0 AN0 — RA1 AN1 — RA2 AN2 V - REF DACOUT RA3 AN3 V + REF RA4 3 ...
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... Packaging Information.............................................................................................................................................................. 385 Appendix A: Revision History............................................................................................................................................................. 397 Appendix B: Device Differences......................................................................................................................................................... 397 Index .................................................................................................................................................................................................. 399 The Microchip Web Site ..................................................................................................................................................................... 407 Customer Change Notification Service .............................................................................................................................................. 407 Customer Support .............................................................................................................................................................................. 407 Reader Response .............................................................................................................................................................................. 408 Product Identification System............................................................................................................................................................. 409 DS41453B-page 8 ) ................................................................................................................................ 329 ™ Preliminary 2011 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com 2011 Microchip Technology Inc. PIC16(L)F1847 to receive the most current information on all of our products. Preliminary DS41453B-page 9 ...
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... PIC16(L)F1847 NOTES: DS41453B-page 10 Preliminary 2011 Microchip Technology Inc. ...
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... Reference Clock Module SR Latch Capture/Compare/PWM Modules ECCP1 ECCP2 CCP3 CCP4 Comparators Master Synchronous Serial Ports MSSP1 MSSP2 Timers Timer0 Timer1 Timer2 Timer4 Timer6 2011 Microchip Technology Inc. of the ● ● ● ● ● ● ● ● ● ● ● ● C1 ● ...
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... See applicable chapters for more information on peripherals. Note 1: See Table 1-1 for peripherals available on specific devices. 2: DS41453B-page 12 Program Flash Memory RAM CPU (Figure 2-1) Timer2- Timer1 DAC Comparators Types Modulator FVR EUSART CapSense Preliminary EEPROM PORTA PORTB 2011 Microchip Technology Inc. ...
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... Legend Analog input or output CMOS = CMOS compatible input or output TTL = TTL compatible input High Voltage XTAL = Crystal Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register. 2: Default function location. 2011 Microchip Technology Inc. Input Output Type Type TTL CMOS General purpose I/O. ...
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... CMOS USART synchronous data C™ C™ data input/output 2. ST — SPI data input 2. — CMOS SPI data output 1. = Schmitt Trigger input with CMOS levels I Preliminary Description OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels 2011 Microchip Technology Inc. ...
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... Legend Analog input or output CMOS = CMOS compatible input or output TTL = TTL compatible input High Voltage XTAL = Crystal Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register. 2: Default function location. 2011 Microchip Technology Inc. PIC16(L)F1847 Input Output Type Type TTL CMOS General purpose I/O ...
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... Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register. 2: Default function location. DS41453B-page 16 Input Output Type Type Power — Ground reference. = Schmitt Trigger input with CMOS levels I Preliminary Description OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels 2011 Microchip Technology Inc. ...
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... Section 3.4 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 29.0 “Instruction Set Summary” details. 2011 Microchip Technology Inc. PIC16(L)F1847 Saving”, for more for more Preliminary DS41453B-page 17 ...
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... Power-up Timer Oscillator Start-up Timer ALU ALU ALU Power- Reset Watchdog W reg Timer Brown-out Reset Preliminary RAM Addr 12 Indirect Addr 12 FSR0 Reg FSR reg FSR reg STATUS Reg STATUS reg STATUS reg MUX MUX MUX 2011 Microchip Technology Inc. ...
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... Program Memory Control”. TABLE 3-1: DEVICE SIZES AND ADDRESSES Device PIC16(L)F1847 2011 Microchip Technology Inc. The following features are associated with access and control of program memory and data memory: • PCL and PCLATH • Stack • Indirect Addressing 3.1 ...
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... MOVWF FSR1H MOVIW 0[FSR1] ;THE PROGRAM MEMORY Preliminary Example 3-1. RETLW INSTRUCTION ;Add Index ;program counter to ;select data ;Index0 data ;Index1 data DATA_INDEX Example 3-2 demonstrates access- ACCESSING PROGRAM MEMORY VIA FSR ;Index0 data ;Index1 data 2011 Microchip Technology Inc. ...
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... WREG • PCLATH • INTCON The core registers are the first 12 Note: addresses of every data memory bank. 2011 Microchip Technology Inc. PIC16(L)F1847 3.2.1.1 STATUS Register The STATUS register, shown in • the arithmetic status of the ALU • the Reset status The STATUS register can be the destination for any instruction, like any other register ...
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... For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. DS41453B-page 22 R-1/q R-1/q R/W-0 Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets q = Value depends on condition (1) Preliminary R/W-0/u R/W-0/u (1) ( bit 0 2011 Microchip Technology Inc. ...
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... General Purpose RAM (80 bytes maximum) 6Fh 70h Common RAM (16 bytes) 7Fh 2011 Microchip Technology Inc. 3.2.5 DEVICE MEMORY MAPS The memory maps for the device family are as shown in Table 3-2. TABLE 3-2: Device PIC16F/LF1847 Section 3.5.2 ...
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TABLE 3-3: PIC16F/LF1847 MEMORY MAP, BANKS 0-7 BANK 0 BANK 1 000h INDF0 080h INDF0 100h 001h INDF1 081h INDF1 101h 002h PCL 082h PCL 102h 003h STATUS 083h STATUS 103h 004h FSR0L 084h FSR0L 104h 005h FSR0H 085h FSR0H ...
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TABLE 3-4: PIC16F/LF1847 MEMORY MAP, BANKS 8-15 BANK 8 BANK 9 400h INDF0 480h INDF0 500h 401h INDF1 481h INDF1 501h 402h PCL 482h PCL 502h 403h STATUS 483h STATUS 503h 404h FSR0L 484h FSR0L 504h 405h FSR0H 485h FSR0H ...
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TABLE 3-5: PIC16F/LF1847 MEMORY MAP, BANKS 16-23’ BANK 16 BANK 17 800h INDF0 880h INDF0 900h 801h INDF1 881h INDF1 901h 802h PCL 882h PCL 902h 803h STATUS 883h STATUS 903h 804h FSR0L 884h FSR0L 904h 805h FSR0H 885h FSR0H ...
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TABLE 3-6: PIC16F/LF1847 MEMORY MAP, BANKS 24-31 BANK 24 BANK 25 C00h INDF0 C80h INDF0 D00h C01h INDF1 C81h INDF1 D01h C02h PCL C82h PCL D02h C03h STATUS C83h STATUS D03h C04h FSR0L C84h FSR0L D04h C05h FSR0H C85h FSR0H ...
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... FEDh STKPTR FEEh TOSL FEFh TOSH = Unimplemented data memory locations, Legend: read as ‘0’. DS41453B-page 28 3.2.6 SPECIAL FUNCTION REGISTERS SUMMARY The Special Function Register Summary for the device family are as follows: Device PIC16(L)F1847 Preliminary 2011 Microchip Technology Inc. Bank(s) Page No ...
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... CPSRM 01Fh CPSCON1 — — unknown unchanged value depends on condition unimplemented reserved. Legend: Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1847 Bit 5 Bit 4 Bit 3 Bit 2 — — BSR4 ...
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... SCS1 SCS0 0011 1-00 0011 1-00 LFIOFR HFIOFS 10q0 0q00 qqqq qq0q xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu GO/DONE ADON -000 0000 -000 0000 ADPREF<1:0> 0000 -000 0000 -000 — — 2011 Microchip Technology Inc. ...
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... Unimplemented x = unknown unchanged value depends on condition unimplemented reserved. Legend: Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1847 Bit 5 Bit 4 Bit 3 Bit 2 — — BSR4 ...
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... OERR RX9D 0000 000x 0000 000x TRMT TX9D 0000 0010 0000 0010 WUE ABDEN 01-0 0-00 01-0 0-00 2011 Microchip Technology Inc. ...
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... ACKSTAT 21Fh SSP2CON3 ACKTIM PCIE x = unknown unchanged value depends on condition unimplemented reserved. Legend: Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1847 Bit 5 Bit 4 Bit 3 Bit 2 — — BSR4 ...
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... PSS2BD<1:0> 0000 0000 0000 0000 STR2B STR2A ---0 0001 ---0 0001 C1TSEL<1:0> 0000 0000 0000 0000 — — 2011 Microchip Technology Inc. ...
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... Unimplemented 31Fh — Unimplemented x = unknown unchanged value depends on condition unimplemented reserved. Legend: Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1847 Bit 5 Bit 4 Bit 3 Bit 2 — — BSR4 ...
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... IOCBF1 IOCBF0 0000 0000 0000 0000 — — — — — — CLKRDIV<2:0> 0011 0000 0011 0000 — — — MDBIT 0010 ---0 0010 ---0 x--- xxxx u--- uuuu xxx- xxxx uuu- uuuu xxx- xxxx uuu- uuuu 2011 Microchip Technology Inc. ...
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... T6CON — 41Fh — Unimplemented x = unknown unchanged value depends on condition unimplemented reserved. Legend: Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1847 Bit 5 Bit 4 Bit 3 Bit 2 — — BSR4 ...
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... BSR1 BSR0 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF IOCF 0000 000x 0000 000u — — 2011 Microchip Technology Inc. ...
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... FEFh — Top-of-Stack High byte TOSH x = unknown unchanged value depends on condition unimplemented reserved. Legend: Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1847 Bit 5 Bit 4 Bit 3 Bit 2 — — ...
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... If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will 0 be loaded with the address BRW If using BRA, the entire PC will be loaded with the signed value of the operand of the BRA instruction. 0 BRA Preliminary 2011 Microchip Technology Inc. ...
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... RETFIE instructions or the vectoring to an interrupt address. FIGURE 3-4: ACCESSING THE STACK EXAMPLE 1 TOSH:TOSL TOSH:TOSL 2011 Microchip Technology Inc. PIC16(L)F1847 3.4.1 ACCESSING THE STACK The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack ...
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... STKPTR = 0x06 0x06 Return Address 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address Return Address 0x00 Preliminary or a single interrupt. instruction is executed, the s, or six s and an instructions 2011 Microchip Technology Inc. ...
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... The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions: • Traditional Data Memory • Linear Data Memory • Program Flash Memory 2011 Microchip Technology Inc. PIC16(L)F1847 Return Address 0x0F 0x0E Return Address ...
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... Not all memory regions are completely implemented. Consult device memory tables for memory limits. Note: DS41453B-page 44 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 Reserved 0x7FFF 0x8000 0x0000 Program Flash Memory 0xFFFF 0x7FFF Preliminary 2011 Microchip Technology Inc. ...
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... SFR, GPR and common registers. FIGURE 3-9: TRADITIONAL DATA MEMORY MAP Direct Addressing From Opcode 4 BSR 6 0 Location Select Bank Select 0x00 0x7F 2011 Microchip Technology Inc FSRxH Bank Select 0000 0001 0010 1111 Bank 0 Bank 1 Bank 2 Bank 31 ...
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... FIGURE 3-11: 7 FSRnH 0 1 Location Select 0x020 Bank 0 0x06F 0x0A0 Bank 1 0x0EF 0x120 Bank 2 0x16F 0xF20 Bank 30 0xF6F Preliminary the FSR/INDF interface. All PROGRAM FLASH MEMORY MAP FSRnL 0x8000 0x0000 Program Flash Memory (low 8 bits) 0x7FFF 0xFFFF 2011 Microchip Technology Inc. ...
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... These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. The DEBUG bit in Configuration Word is Note: managed automatically development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’. 2011 Microchip Technology Inc. by device Preliminary PIC16(L)F1847 DS41453B-page 47 ...
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... WDTE0 U = Unimplemented bit, read as ‘1’ -n/n = Value at POR and BOR/Value at all other Resets P = Programmable bit (1) (2) Pin Function Select bit (1) Preliminary R/P-1/1 R/P-1/1 R/P-1/1 BOREN1 BOREN0 CPD bit 8 R/P-1/1 R/P-1/1 R/P-1/1 FOSC2 FOSC1 FOSC0 bit 0 2011 Microchip Technology Inc. ...
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... Enabling Brown-out Reset does not automatically enable Power-up Timer. Note 1: The entire data EEPROM will be erased when the code protection is disabled during an erase. 2: The entire program memory will be erased when the code protection is disabled during an erase. 3: 2011 Microchip Technology Inc. PIC16(L)F1847 Preliminary DS41453B-page 49 ...
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... R/P-1/1 R/P-1/1 — BORV STVREN R-1 U-1 U-1 — — Unimplemented bit, read as ‘1’ -n/n = Value at POR and BOR/Value at all other Resets P = Programmable bit (1) (2) Preliminary R/P-1/1 U-1 PLLEN — bit 7 R/P-1/1 R/P-1/1 WRT<1:0> bit 0 2011 Microchip Technology Inc. ...
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... See Section 11.5 “User ID, Device ID and Configuration for more information on accessing Word Access” these memory locations. For more information on checksum calculation, “PIC16F/LF1847/PIC12F/LF1840 Programming Specification” (DS41439). 2011 Microchip Technology Inc. “Write see the Memory Preliminary PIC16(L)F1847 DS41453B-page 51 ...
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... Legend Readable bit -n = Value at POR bit 15-14 Unimplemented: Read as ‘1’ bit 13-5 DEV<8:0>: Device ID bits 010100100 = PIC16F1847 010100101 = PIC16LF1847 bit 4-0 REV<4:0>: Revision ID bits These bits are used to identify the revision. This location cannot be written. Note 1: DS41453B-page 52 (1) R/P-1 ...
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... XT, HS modes) and switch automatically to the internal oscillator. • Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources 2011 Microchip Technology Inc. PIC16(L)F1847 The oscillator module can be configured in one of eight clock modes. 1. ECL – External Clock Low Power mode (0 MHz to 0 ...
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... WDT, PWRT, Fail-Safe Clock Monitor Two-Speed Start-up and other modules Preliminary Sleep CPU and T1OSC Peripherals Clock Control FOSC<2:0> SCS<1:0> Clock Source Option for other modules 2011 Microchip Technology Inc. ...
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... High power, 4-32 MHz (FOSC = 111) • Medium power, 0.5-4 MHz (FOSC = 110) • Low power, 0-0.5 MHz (FOSC = 101) 2011 Microchip Technology Inc. The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep ...
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... Preliminary CERAMIC RESONATOR OPERATION ( MODE) ® PIC MCU OSC1/CLKIN To Internal Logic R (3) ( Sleep F OSC2/CLKOUT R S (1) ) may be required for S varies with the Oscillator mode F P Oscillator Start-up Timer (OST) Section 5.4 Mode”). 4xPLL Specifications in Section 30.0 2011 Microchip Technology Inc. ) ...
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... MS1V-T1K 32.768 kHz Tuning Fork Crystal to a PIC16F690/SS” (DS91097) • AN1288, “Design Practices for Low-Power External Oscillators” (DS01288) 2011 Microchip Technology Inc. 5.2.1.6 The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required ...
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... OSCSTAT register indicates when the MFINTOSC is running and can be utilized. Preliminary (Register 5-3). Figure 5-1). One of nine Section 5.2.2.7 “Internal for more information. Internal Oscillator Figure 5-1). One of nine Section 5.2.2.7 “Internal for more information. 2011 Microchip Technology Inc. ...
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... Watchdog Timer (WDT) • Fail-Safe Clock Monitor (FSCM) The Low-Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running and can be utilized. 2011 Microchip Technology Inc. PIC16(L)F1847 5.2.2.5 Internal Oscillator Frequency Selection The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits 5-3) ...
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... Clock switching time delays are shown in Start-up delay specifications are located in the oscillator tables of Specifications”. Preliminary 2011 Microchip Technology Inc. Figure 5-6). If this is the Table 5-1. Section 30.0 “Electrical ...
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... IRCF <3:0> System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC Start-up Time HFINTOSC/ MFINTOSC IRCF <3:0> System Clock 2011 Microchip Technology Inc. Start-up Time 2-cycle Sync 0 2-cycle Sync LFINTOSC turns off unless WDT or FSCM is enabled 2-cycle Sync 0 Preliminary ...
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... The Timer1 Oscillator Ready (T1OSCR) bit of the OSCSTAT register indicates whether the Timer1 oscillator is ready to be used. After the T1OSCR bit is set, the SCS bits can be configured to select the Timer1 oscillator. Start-up or Preliminary Section 21.0 for more 2011 Microchip Technology Inc. ...
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... LFINTOSC Any clock source Timer1 Oscillator PLL inactive PLL active PLL inactive. Note 1: 2011 Microchip Technology Inc. 5.4.1 TWO-SPEED START-UP MODE CONFIGURATION Two-Speed Start-up mode is configured by the following settings: • IESO (of the Configuration Word Inter- nal/External Switchover bit (Two-Speed Start-up mode enabled). • ...
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... CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCSTAT register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word 1, or the internal oscillator Preliminary 2011 Microchip Technology Inc. ...
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... The internal clock source chosen by the FSCM is determined by the IRCF<3:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs. 2011 Microchip Technology Inc. 5.5.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or changing the SCS bits of the OSCCON register ...
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... Clock Monitor Output (Q) OSCFIF The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in Note: this example have been chosen for clarity. DS41453B-page 66 Oscillator Failure Test Test Preliminary Failure Detected Test 2011 Microchip Technology Inc. ...
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... SCS<1:0>: System Clock Select bits 1x = Internal oscillator block 01 = Timer1 oscillator 00 = Clock determined by FOSC<2:0> in Configuration Word 1. Duplicate frequency derived from HFINTOSC. Note 1: 2011 Microchip Technology Inc. R/W-1/1 R/W-1/1 IRCF<3:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Section 5 ...
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... HFINTOSC is at least 0.5% accurate 0 = HFINTOSC is not 0.5% accurate DS41453B-page 68 R-0/q R-0/q R-q/q HFIOFR HFIOFL MFIOFR U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets q = Conditional Preliminary R-0/0 R-0/q LFIOFR HFIOFS bit 0 2011 Microchip Technology Inc. ...
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... CONFIG1 7:0 CP MCLRE — = unimplemented locations read as ‘0’. Shaded cells are not used by clock sources. Legend: 2011 Microchip Technology Inc. R/W-0/0 R/W-0/0 R/W-0/0 TUN<5:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Bit 5 ...
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... PIC16(L)F1847 NOTES: DS41453B-page 70 Preliminary 2011 Microchip Technology Inc. ...
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... Upon any device Reset, the reference clock module is disabled. The user’s firmware is responsible for initializing the module before enabling the output. The registers are reset to their default values. 2011 Microchip Technology Inc. PIC16(L)F1847 6.3 Conflicts with the CLKR pin ...
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... DS41453B-page 72 R/W-1/1 R/W-0/0 R/W-0/0 CLKRDC<1:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (3) (1) (2) /4. See Section 6.3 “Conflicts with the CLKR pin” Preliminary R/W-0/0 R/W-0/0 CLKRDIV<2:0> bit 0 for details. 2011 Microchip Technology Inc. ...
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... Bit -/6 13:8 — — CONFIG1 7:0 CP MCLRE — = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources. Legend: 2011 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 CLKRDC<1:0> Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 FCMEN ...
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... PIC16(L)F1847 NOTES: DS41453B-page 74 Preliminary 2011 Microchip Technology Inc. ...
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... SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Programming Mode Exit RESET Instruction Stack Overflow/Underflow Reset Stack Pointer External Reset MCLRE MCLR Sleep WDT Time-out Power-on Reset V DD Brown-out Reset BOR Enable 2011 Microchip Technology Inc. PIC16(L)F1847 PWRT Zero 64 ms LFINTOSC PWRTEN Preliminary Device Reset DS41453B-page 75 ...
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... V for a DD BOR , the device BORDC for more information. Device Device Operation upon Operation upon wake- up from release of POR Sleep (1) Waits for BOR ready Waits for BOR ready Begins immediately Begins immediately Begins immediately level. DD 2011 Microchip Technology Inc. ...
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... If BOREN <1:0> in Configuration Word BOR Enabled 0 = BOR Disabled bit 6-1 Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive 2011 Microchip Technology Inc. PIC16(L)F1847 T BORRDY BOR Protection Active (1) T PWRT < T ...
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... Power-up Timer and oscillator start-up timer will expire. Upon bringing MCLR high, the device will begin execution immediately (see is useful for testing purposes or to synchronize more than one device operating in parallel. Section 10.0 Table 7-4 for Preliminary Figure 7-4). This 2011 Microchip Technology Inc. ...
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... FIGURE 7-4: RESET START-UP SEQUENCE V DD Internal POR Power-Up Timer MCLR Internal RESET Oscillator Modes External Crystal Oscillator Start-Up Timer Oscillator F OSC Internal Oscillator Oscillator F OSC External Clock (EC) CLKIN F OSC 2011 Microchip Technology Inc. PIC16(L)F1847 T PWRT T MCLR T OST Preliminary DS41453B-page 79 ...
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... Program Counter 0000h ---1 1000 0000h ---u uuuu 0000h ---1 0uuu 0000h ---0 uuuu ---0 0uuu 0000h ---1 1uuu ( ---1 0uuu 0000h ---u uuuu 0000h ---u uuuu 0000h ---u uuuu Preliminary Condition STATUS PCON Register Register 00-- 110x uu-- 0uuu uu-- 0uuu uu-- uuuu uu-- uuuu 00-- 11u0 uu-- uuuu uu-- u0uu 1u-- uuuu u1-- uuuu 2011 Microchip Technology Inc. ...
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... A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) 2011 Microchip Technology Inc. PIC16(L)F1847 7-2. U-0 R/W/HC-1/q R/W/HC-1/q — ...
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... Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. Note 1: DS41453B-page 82 Bit 5 Bit 4 Bit 3 Bit 2 — — — — — — RMCLR RI — Preliminary Register Bit 1 Bit 0 on Page — BORRDY 77 POR BOR 103 2011 Microchip Technology Inc. ...
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... A block diagram of the interrupt logic is shown in Figure 8-1 and Figure 8-2. FIGURE 8-1: INTERRUPT LOGIC TMR0IF TMR0IE From Peripheral Interrupt Logic (Figure 8-2) 2011 Microchip Technology Inc. Wake-up (If in Sleep mode) INTF INTE IOCF IOCE PEIE GIE Preliminary PIC16(L)F1847 Interrupt to CPU DS41453B-page 83 ...
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... OSFIE C2IF C2IE C1IF C1IE EEIF EEIE BCL1IF BCL1IE (1) CCP2IF (1) CCP2IE (1) CCP4IF (1) CCP4IE (1) CCP3IF (1) CCP3IE (1) TMR6IF (1) TMR6IE (1) TMR4IF (1) TMR4IE (1) BCL2IF (1) BCL2IE (1) SSP2IF (1) SSP2IE Note 1: These interrupts are available on PIC16F/LF1827 only DS41453B-page 84 Preliminary 2011 Microchip Technology Inc. To Interrupt Logic (Figure 5-1) ...
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... All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again. 2011 Microchip Technology Inc. PIC16(L)F1847 8.2 Interrupt Latency Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins ...
Page 86
... Inst(PC) NOP NOP PC+1/FSR New PC/ 0004h ADDR PC+1 Inst(PC) NOP NOP PC+1 PC+2 INST(PC) NOP NOP PC+1 PC+2 INST(PC) NOP NOP Preliminary 0005h Inst(0004h) 0005h Inst(0004h) 0004h 0005h NOP Inst(0004h) Inst(0005h) 0004h 0005h NOP NOP Inst(0004h) 2011 Microchip Technology Inc. ...
Page 87
... Asynchronous interrupt latency = 3-5 T Latency is the same whether Inst (PC single cycle or a 2-cycle instruction. 3: CLKOUT not available in all oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in 5: INTF is enabled to be set any time during the Q4-Q1 cycles. 2011 Microchip Technology Inc ...
Page 88
... Shadow register should be modified and the value will be restored when exiting the ISR. The Shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s appli- cation, other registers may also need to be saved. DS41453B-page 88 Preliminary 2011 Microchip Technology Inc. ...
Page 89
... None of the interrupt-on-change pins have changed state The IOCF Flag bit is read-only and cleared when all the interrupt-on-change flags in the IOCBF register Note 1: have been cleared by software. 2011 Microchip Technology Inc. PIC16(L)F1847 Interrupt flag bits are set when an interrupt Note: ...
Page 90
... Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 R/W-0/0 TXIE SSP1IE CCP1IE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 TMR2IE TMR1IE bit 0 2011 Microchip Technology Inc. ...
Page 91
... Disables the MSSP1 Bus Collision Interrupt bit 2-1 Unimplemented: Read as ‘0’ bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt 2011 Microchip Technology Inc. PIC16(L)F1847 Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 ...
Page 92
... Note 1: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 U-0 CCP3IE TMR6IE — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 U-0 TMR4IE — bit 0 2011 Microchip Technology Inc. ...
Page 93
... Disables the MSSP2 Bus Collision Interrupt bit 0 SSP2IE: Master Synchronous Serial Port 2 (MSSP2) Interrupt Enable bit 1 = Enables the MSSP2 interrupt 0 = Disables the MSSP2 interrupt 2011 Microchip Technology Inc. PIC16(L)F1847 Note 1: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. U-0 ...
Page 94
... R-0/0 R/W-0/0 R/W-0/0 TXIF SSP1IF CCP1IF U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary 2011 Microchip Technology Inc. should ensure the R/W-0/0 R/W-0/0 TMR2IF TMR1IF bit 0 ...
Page 95
... Unimplemented: Read as ‘0’ bit 0 CCP2IF: CCP2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending 2011 Microchip Technology Inc. PIC16(L)F1847 Interrupt flag bits are set when an interrupt Note: condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register ...
Page 96
... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. R/W-0/0 R/W-0/0 U-0 CCP3IF TMR6IF — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 U-0 TMR4IF — bit 0 2011 Microchip Technology Inc. ...
Page 97
... Shaded cells are not used by Interrupts. Legend: 2011 Microchip Technology Inc. Note 1: Interrupt flag bits are set when an inter- rupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register ...
Page 98
... PIC16(L)F1847 NOTES: DS41453B-page 98 Preliminary 2011 Microchip Technology Inc. ...
Page 99
... Converter (DAC) Module” Section 14.0 “Fixed for more information on Voltage Reference (FVR)” these modules. 2011 Microchip Technology Inc. PIC16(L)F1847 9.1 Wake-up from Sleep The device can wake-up from Sleep through one of the following events: 1. External Reset input on MCLR pin, if enabled 2 ...
Page 100
... Inst(0004h) Inst(0005h) Dummy Cycle Inst(0004h) Register on Bit 1 Bit 0 Page INTF IOCF 89 IOCBF1 IOCBF0 132 IOCBN1 IOCBN0 132 IOCBP1 IOCBP0 132 TMR2IE TMR1IE 90 — CCP2IE 91 BCL2IE SSP2IE 93 TMR2IF TMR1IF 94 — CCP2IF 95 BCL2IF SSP2IF WDTPS0 SWDTEN 103 2011 Microchip Technology Inc. ...
Page 101
... Configurable time-out period is from 256 seconds (typical) • Multiple Reset conditions • Operation during Sleep FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0> SWDTEN WDTE<1:0> WDTE<1:0> Sleep 2011 Microchip Technology Inc. PIC1(L)F1847 23-bit Programmable LFINTOSC Prescaler WDT WDTPS<4:0> Preliminary WDT Time-out DS41453B-page 101 ...
Page 102
... STATUS register are changed to indicate the Active event. See Section 3.0 “Memory Organization” Active more information. Disabled Active Disabled Disabled Preliminary Section 5.0 “Oscillator for more for WDT Cleared Cleared until the end of OST Unaffected 2011 Microchip Technology Inc. ...
Page 103
... SWDTEN: Software Enable/Disable for Watchdog Timer bit If WDTE<1:0> = 00: This bit is ignored. If WDTE<1:0> WDT is turned WDT is turned off If WDTE<1:0> = 1x: This bit is ignored. 2011 Microchip Technology Inc. R/W-1/1 R/W-0/0 R/W-1/1 WDTPS<4:0> Unimplemented bit, read as ‘0’ -m/n = Value at POR and BOR/Value at all other Resets 17 ...
Page 104
... PIC1(L)F1847 NOTES: DS41453B-page 104 Preliminary 2011 Microchip Technology Inc. ...
Page 105
... When code-protected, the CPU may continue to read and write the data EEPROM memory and Flash program memory. 2011 Microchip Technology Inc. PIC16(L)F1847 11.1 EEADRL and EEADRH Registers The EEADRH:EEADRL register pair can address maximum of 256 bytes of data EEPROM maximum of 32K words of program memory ...
Page 106
... CPU is able to read and write data to the data EEPROM recommended to code-protect the pro- gram memory when code-protecting data memory. This prevents anyone from replacing your program with a program that will access the contents of the data EEPROM. Preliminary 2011 Microchip Technology Inc. (Register 4-1) ...
Page 107
... FLASH PROGRAM MEMORY READ CYCLE EXECUTION Flash ADDR Flash Data INSTR (PC) INSTR( BSF EECON1,RD executed here executed here RD bit EEDATH EEDATL Register EERHLT 2011 Microchip Technology Inc. PIC16(L)F1847 EEADRH,EEADRL PC+3 INSTR ( EEDATH,EEDATL INSTR ( INSTR( Forced NOP executed here executed here Preliminary INSTR ( ...
Page 108
... Note 1: The two instructions following a program memory read are required to be NOPs. This prevents the user from executing a two-cycle instruction after the RD bit is set. 2: Flash program memory can be read regardless of the setting of the CP bit. Number of Write Latches 32 Preliminary instruction on the next 2011 Microchip Technology Inc. ...
Page 109
... NOP ; Executed NOP ; Ignored BSF INTCON,GIE ; Restore interrupts MOVF EEDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF EEDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location 2011 Microchip Technology Inc. PIC16(L)F1847 (Figure 11-1) (Figure 11-1) Preliminary DS41453B-page 109 ...
Page 110
... If the number of write latches is smaller Note: than the erase block size, the code sequence provided in be repeated multiple times to fully program an erased program memory row. Preliminary 2011 Microchip Technology Inc. 11-5. The initial address is Example 11-5 must ...
Page 111
... EEADRL<4:0> = 00000 EEADRL<4:0> = 00001 Buffer Register 2011 Microchip Technology Inc. continue to run. The processor does not stall when LWLO = 1, loading the write latches. After the write cycle, the processor will resume operation with the third instruction after the EECON1 write instruction. ...
Page 112
... Write AAh ; Set WR bit to begin erase ; Any instructions here are ignored as processor ; halts to begin erase sequence ; Processor will stop here and wait for erase complete. ; after erase processor continues with 3rd instruction ; Disable writes ; Enable interrupts Preliminary 2011 Microchip Technology Inc. ...
Page 113
... EECON2 MOVLW 0AAh MOVWF EECON2 BSF EECON1,WR NOP NOP BCF EECON1,WREN BSF INTCON,GIE 2011 Microchip Technology Inc. PIC16(L)F1847 ; Disable ints so required sequences will execute properly ; Bank 3 ; Load initial address ; ; ; ; Load initial data address ; ; ; Point to program memory ; Not configuration space ; Enable writes ...
Page 114
... Table When read access is initiated on an address outside the parameters listed in register pair is cleared. Function Read Access User IDs Yes Yes Yes Figure 11-1) Figure 11-1) Preliminary 11-2. Table 11-2, the EEDATH:EEDATL Write Access Yes No No 2011 Microchip Technology Inc. ...
Page 115
... EEPROM WRITE VERIFY BANKSEL EEDATL ; MOVF EEDATL, W ;EEDATL not changed ;from previous write BSF EECON1, RD ;YES, Read the ;value written XORWF EEDATL BTFSS STATUS, Z ;Is data the same GOTO WRITE_ERR ;No, handle error : ;Yes, continue 2011 Microchip Technology Inc. PIC16(L)F1847 Preliminary DS41453B-page 115 ...
Page 116
... Value at POR and BOR/Value at all other Resets R/W-0/0 R/W-0/0 R/W-0/0 EEADR<14:8> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u bit 0 R/W-x/u R/W-x/u bit 0 R/W-0/0 R/W-0/0 bit 0 R/W-0/0 R/W-0/0 bit 0 2011 Microchip Technology Inc. ...
Page 117
... RD: Read Control bit 1 = Initiates an program Flash or data EEPROM read. Read takes one cycle cleared in hardware. The RD bit can only be set (not cleared) in software Does not initiate a program Flash or data EEPROM data read. 2011 Microchip Technology Inc. PIC16(L)F1847 R/W/HC-0/0 R/W-x/q R/W-0/0 ...
Page 118
... Bit 3 Bit 2 FREE WRERR WREN INTE IOCE TMR0IF EEIE BCL1IE — EEIF BCL1IF — Preliminary W-0/0 W-0/0 bit 0 Register Bit 1 Bit 0 on Page WR RD 117 118 116 116 116 116 INTF IOCF 89 — CCP2IE 91 — CCP2IF 95 2011 Microchip Technology Inc. ...
Page 119
... Write PORTx CK Data Register Data Bus Read PORTx To peripherals ANSELx 2011 Microchip Technology Inc. PIC16(L)F1847 12.1 Alternate Pin Function The Alternate Pin Function Control (APFCON0 and APFCON1) registers are used to steer specific peripheral input and output functions between different pins. The APFCON0 and APFCON1 registers are ...
Page 120
... Value at POR and BOR/Value at all other Resets U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 P1CSEL CCP1SEL bit 0 U-0 R/W-0/0 — TXCKSEL bit 0 2011 Microchip Technology Inc. ...
Page 121
... Power-on Reset by the WPUEN OPTION_REG register. 2011 Microchip Technology Inc. 12.2.2 ANSELA REGISTER The ANSELA register configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELA bit high will cause all digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly ...
Page 122
... R/W-x/u R/W-x/u R/W-x/u LATA4 LATA3 LATA2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) (1) Preliminary R/W-x/x R/W-x/x RA1 RA0 bit 0 R/W-1/1 R/W-1/1 TRISA1 TRISA0 bit 0 R/W-x/u R/W-x/u LATA1 LATA0 bit 0 2011 Microchip Technology Inc. ...
Page 123
... Digital I/O. Pin is assigned to port or digital special function Analog input. Pin is assigned as analog input When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to Note 1: allow external control of the voltage on the pin. 2011 Microchip Technology Inc. PIC16(L)F1847 U-0 U-0 U-0 — ...
Page 124
... RA3 RA4 1. SRNQ (SR latch) 2. CCP4 3. T0CKI 4. C2OUT (Comparator) 5. RA4 DS41453B-page 124 RA5 Input only pin. RA6 1. OSC2 (enabled by Configuration Word) 2. CLKOUT 3. CLKR 4. SDO1 5. P1D 6. P2B 7. RA6 RA7 1. OSC1/CLKIN (enabled by Configuration Word) 2. P1C 3. CCP2 4. P2A 5. RA7 Preliminary 2011 Microchip Technology Inc. ...
Page 125
... Name Bits Bit -/7 Bit -/6 13:8 — — CONFIG1 7:0 CP MCLRE — = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. Legend: 2011 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 — ANSA4 ANSA3 ANSA2 LATA4 LATA3 LATA2 — TMR0CS ...
Page 126
... I/O pins configured as analog input always read ‘0’. The ANSELB register must be initialized Note: to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’. Section 13.0 Preliminary (Register 12-12) is used to (Register 12-9) controls the PORTB 2011 Microchip Technology Inc. ...
Page 127
... Bit is cleared bit 7-0 LATB<7:0>: PORTB Output Latch Value bits Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is Note 1: return of actual I/O pin values. 2011 Microchip Technology Inc. PIC16(L)F1847 R/W-x/x R/W-x/x R/W-x/x RB4 RB3 RB2 U = Unimplemented bit, read as ‘ ...
Page 128
... Value at POR and BOR/Value at all other Resets R/W-1/1 R/W-1/1 R/W-1/1 ANSB4 ANSB3 ANSB2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) . Digital input buffer disabled. Preliminary R/W-1/1 R/W-1/1 WPUB1 WPUB0 bit 0 R/W-1/1 U-0 ANSB1 — bit 0 2011 Microchip Technology Inc. ...
Page 129
... RB0 1. P1A 2. RB0 RB1 1. SDA1 2. RX/DT 3. RB1 RB2 1. SDA2 2. TX/CK 3. RX/DT 4. SDO1 5. RB2 2011 Microchip Technology Inc. PIC16(L)F1847 RB3 1. MDOUT 2. CCP1/P1A 3. RB3 RB4 1. SCL1 2. SCK1 3. RB4 RB5 1. SCL2 2. TX/CK 3. SCK2 4. P1B 5 ...
Page 130
... RB3 TRISB5 TRISB4 TRISB3 WPUB5 WPUB4 WPUB3 Preliminary Register Bit 2 Bit 1 Bit 0 on Page ANSB2 ANSB1 — 128 LATB2 LATB1 LATB0 127 PS<2:0> 177 RB2 RB1 RB0 127 TRISB2 TRISB1 TRISB0 127 WPUB2 WPUB1 WPUB0 128 2011 Microchip Technology Inc. ...
Page 131
... RBx IOCBPx 2011 Microchip Technology Inc. 13.3 Interrupt Flags The IOCBFx bits located in the IOCBF register are status flags that correspond to the Interrupt-on-change pins of the port expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the IOCE interrupt ...
Page 132
... R/W/HS-0/0 IOCBF4 IOCBF3 IOCBF2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets HS - Bit is set in hardware Preliminary R/W-0/0 R/W-0/0 IOCBP1 IOCBP0 bit 0 R/W-0/0 R/W-0/0 IOCBN1 IOCBN0 bit 0 R/W/HS-0/0 R/W/HS-0/0 IOCBF1 IOCBF0 bit 0 2011 Microchip Technology Inc. ...
Page 133
... IOCBF7 IOCBF6 IOCBN IOCBN7 IOCBN6 IOCBP IOCBP7 IOCBP6 TRISB TRISB7 TRISB6 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by interrupt-on-change. 2011 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 ANSB5 ANSB4 ANSB3 ANSB2 TMR0IE INTE IOCE TMR0IF ...
Page 134
... PIC16(L)F1847 NOTES: DS41453B-page 134 Preliminary 2011 Microchip Technology Inc. ...
Page 135
... FVRCON register. FIGURE 14-1: VOLTAGE REFERENCE BLOCK DIAGRAM ADFVR<1:0> CDAFVR<1:0> FVREN FVRRDY 2011 Microchip Technology Inc. 14.1 Independent Gain Amplifiers The output of the FVR supplied to the ADC, Comparators, and DAC is routed through two independent programmable gain amplifiers. Each , with 1.024V, ...
Page 136
... Value at POR and BOR/Value at all other Resets q = Value depends on condition (1) (3) (3) (Low Range) (High Range for additional information. Bit 5 Bit 4 Bit 3 Bit 2 TSEN TSRNG CDAFVR<1:0> Preliminary R/W-0/0 R/W-0/0 ADFVR<1:0> bit 0 (2) (2) (2) (2) Register Bit 1 Bit 0 on page ADFVR<1:0> 136 2011 Microchip Technology Inc. ...
Page 137
... The low range is selected by clearing the TSRNG bit of the FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation. 2011 Microchip Technology Inc. FIGURE 15-1: 15.2 Minimum Operating V Minimum Sensing Temperature ...
Page 138
... PIC16(L)F1847 NOTES: DS41453B-page 138 Preliminary 2011 Microchip Technology Inc. ...
Page 139
... Temp Indicator DAC FVR Buffer1 CHS<4:0> When ADON = 0, all multiplexer inputs are disconnected. Note: 2011 Microchip Technology Inc. The ADC voltage reference is software selectable to be either internally generated or externally supplied. The ADC can generate an interrupt upon completion of (ADC) allows a conversion. This interrupt can be used to wake-up the device from Sleep ...
Page 140
... ADC clock selections. Unless using the F Note: system clock frequency will change the ADC adversely affect the ADC result. Section 16.2 Preliminary peri- AD Figure 16-2. specification AD for more gives examples of appropriate , any changes in the RC clock frequency, which may 2011 Microchip Technology Inc. ...
Page 141
... Sleep mode. FIGURE 16-2: ANALOG-TO-DIGITAL CONVERSION Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit 2011 Microchip Technology Inc DEVICE OPERATING FREQUENCIES AD S Device Frequency (F 20 MHz 16 MHz (2) 100 ns (2) 125 ns (2) (2) (2) (2) 200 ns 250 ns (2) (2) 0.5 ...
Page 142
... ADCON1 register controls the output format. Figure 16-3 shows the two output formats. for more ADRESH LSB bit 0 bit 7 10-bit A/D Result MSB bit 0 bit 7 10-bit A/D Result Preliminary ADRESL bit 0 Unimplemented: Read as ‘0’ LSB bit 0 2011 Microchip Technology Inc. ...
Page 143
... A device Reset forces all registers to their Note: Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. 2011 Microchip Technology Inc. PIC16(L)F1847 16.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the F option ...
Page 144
... MOVF ADRESL,W MOVWF RESULTLO Preliminary A/D CONVERSION ; ;clock ;Vdd and Vss Vref ; ;Set RA0 to input ; ;Set RA0 to analog ; ;Turn ADC On ;Acquisiton delay ;No, test again ; ;Read upper 2 bits ;store in GPR space ; ;Read lower 8 bits ;Store in GPR space 2011 Microchip Technology Inc. ...
Page 145
... ADC is disabled and consumes no operating current See Note 1: Section 17.0 “Digital-to-Analog Converter (DAC) Module” See 2: Section 14.0 “Fixed Voltage Reference (FVR)” 2011 Microchip Technology Inc. PIC16(L)F1847 R/W-0/0 R/W-0/0 R/W-0/0 CHS<4:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (2) for more information ...
Page 146
... U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets SS (1) - pin REF DD (1) + pin REF + pin as the source of the positive reference, be aware that a REF Section 30.0 “Electrical Specifications” Preliminary R/W-0/0 R/W-0/0 ADPREF<1:0> bit 0 for details. 2011 Microchip Technology Inc. ...
Page 147
... Bit is set ‘0’ = Bit is cleared bit 7-6 ADRES<1:0>: ADC Result Register bits Lower 2 bits of 10-bit conversion result bit 5-0 Reserved: Do not use. 2011 Microchip Technology Inc. PIC16(L)F1847 R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 148
... U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u ADRES<7:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u ADRES<9:8> bit 0 R/W-x/u R/W-x/u bit 0 2011 Microchip Technology Inc. ...
Page 149
... The charge holding capacitor (C 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. 2011 Microchip Technology Inc. source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started ...
Page 150
... V - REF DS41453B-page 150 V DD Sampling Switch 0. Rss R IC LEAKAGE (1) I 0. Full-Scale Range 0.5 LSB Zero-Scale Full-Scale Transition V REF Transition Preliminary HOLD REF Sampling Switch (k) Analog Input Voltage 1.5 LSB + 2011 Microchip Technology Inc. ...
Page 151
... TRISB6 FVRCON FVREN FVRRDY DACCON0 DACEN DACLPS DACCON1 — — — = unimplemented read as ‘0’. Shaded cells are not used for ADC module. Legend: 2011 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 CHS<4:0> — ADNREF — ANSA4 ANSA3 ANSA2 ANSB5 ...
Page 152
... PIC16(L)F1847 NOTES: DS41453B-page 152 Preliminary 2011 Microchip Technology Inc. ...
Page 153
... Section 30.0 Specifications”. 2011 Microchip Technology Inc. 17.3 Low Power Voltage State In order for the DAC module to consume the least amount of power, one of the two voltage reference input sources to the resistor ladder must be disconnected. Either the positive voltage source, (V ...
Page 154
... Output Clamped to Positive Voltage Source V + SRC R DACR<4:0> = 11111 R DACEN = 0 DACLPS = 1 DAC Voltage Ladder (see SRC DS41453B-page 154 Output Clamped to Negative Voltage Source V + SRC DACEN = 0 DACLPS = 0 Figure 17- SRC Preliminary R R DAC Voltage Ladder (see Figure 17-2) R DACR<4:0> = 00000 2011 Microchip Technology Inc. ...
Page 155
... V - REF V SS 2011 Microchip Technology Inc. PIC16(L)F1847 digital input threshold detector functions of that pin. Reading the DACOUT pin when it has been configured for DAC reference voltage output will always return a ‘0’. Due to the limited current drive capability, a buffer must be used on the DAC voltage reference output for external connections to DACOUT ...
Page 156
... Effects of a Reset A device Reset affects the following: • DAC is disabled. • DAC output voltage is removed from the DACOUT pin. • The DACR<4:0> range select bits are cleared. DS41453B-page 156 + DACOUT – Preliminary Buffered DAC Output 2011 Microchip Technology Inc. ...
Page 157
... OUT SRC SRC The output select bits are always right justified to ensure that any number of bits can be used without Note 1: affecting the register layout. 2011 Microchip Technology Inc. U-0 R/W-0/0 R/W-0/0 — DACPSS<1:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 158
... Shaded cells are unused with the DAC module. Legend: DS41453B-page 158 Bit 5 Bit 4 Bit 3 Bit 2 TSEN TSRNG CDAFVR<1:0> DACOE — DACPSS<1:0> — DACR<4:0> Preliminary Register Bit 1 Bit 0 on page ADFVR<1:0> 136 — DACNSS 157 157 2011 Microchip Technology Inc. ...
Page 159
... Enabling both the Set and Reset inputs Note: from any one source at the same time may result in indeterminate operation, as the Reset dominance cannot be assured. 2011 Microchip Technology Inc. PIC16(L)F1847 18.2 Latch Output The SRQEN and SRNQEN bits of the SRCON0 regis- ter control the Q and Q latch outputs ...
Page 160
... SRRPE SRCLK SRRCKE (3) SYNCC2OUT SRRC2E (3) SYNCC1OUT SRRC1E and simultaneously Note 1: Pulse generator causes a 1 Q-state pulse width. 2: Name denotes the connection point at the comparator output. 3: DS41453B-page 160 SRLEN SRQEN (1) Latch R Q SRLEN SRNQEN Preliminary 2011 Microchip Technology Inc. SRQ SRNQ ...
Page 161
... Pulse set input for 1 Q-clock period effect on set input. bit 0 SRPR: Pulse Reset Input of the SR Latch bit 1 = Pulse Reset input for 1 Q-clock period effect on Reset input. Set only, always reads back ‘0’. Note 1: 2011 Microchip Technology Inc MHz MHz OSC OSC 39.0 kHz 31 ...
Page 162
... C1 Comparator output has no effect on the Reset input of the SR latch DS41453B-page 162 R/W-0/0 R/W-0/0 R/W-0/0 SRSC1E SRRPE SRRCKE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 SRRC2E SRRC1E bit 0 2011 Microchip Technology Inc. ...
Page 163
... SRCON0 SRLEN SRCLK<2:0> SRCON1 SRSPE SRSCKE TRISA TRISA7 TRISA6 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the SR latch module. 2011 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 — ANSA4 ANSA3 ANSA2 SRQEN SRNQEN SRSC2E SRSC1E ...
Page 164
... PIC16(L)F1847 NOTES: DS41453B-page 164 Preliminary 2011 Microchip Technology Inc. ...
Page 165
... Programmable output polarity • Interrupt-on-change • Wake-up from Sleep • Programmable Speed/Power optimization • PWM shutdown • Programmable and fixed voltage reference 2011 Microchip Technology Inc. PIC16(L)F1847 19.1 Comparator Overview A single comparator is shown in the relationship between the analog input levels and the digital output ...
Page 166
... DS41453B-page 166 (1) Interrupt Interrupt C POL CxHYS D (from Timer1) T1CLK Preliminary CxINTP det Set CxIF CxINTN det C OUT X To Data Bus Q MC OUT X To ECCP PWM Logic C SYNC TRIS bit C OUT Timer1 or SR Latch SYNCC OUT X 2011 Microchip Technology Inc. ...
Page 167
... FVR Buffer2 3 CxON PCH<1:0> When CxON = 0, the Comparator will produce a ‘0’ at the output Note 1: When CxON = 0, all multiplexer inputs are disconnected. 2: Output of comparator can be frozen during debugging. 3: 2011 Microchip Technology Inc. (1) Interrupt Interrupt C POL CxHYS D (from Timer1) T1CLK ...
Page 168
... CxSP control bit. The default state for this bit is ‘1’ which selects the normal speed mode. Device power consumption can be optimized at the cost of slower comparator propaga- tion delay by clearing the CxSP bit to ‘0’. Preliminary 2011 Microchip Technology Inc. CxOUT ...
Page 169
... Block Diagram (Figure 19-2) and the Timer1 Block Diagram (Figure 21-1) for more information. 2011 Microchip Technology Inc. PIC16(L)F1847 19.5 Comparator Interrupt An interrupt can be generated upon a change in the output value of the comparator for each comparator, a rising edge detector and a Falling edge detector are present ...
Page 170
... Pins configured as digital inputs will convert as an analog input, according to the input specification. 2: Analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified. Preliminary 2011 Microchip Technology Inc. and V . The DD SS and V . ...
Page 171
... Input Capacitance PIN I = Leakage Current at the pin due to various junctions LEAKAGE R = Interconnect Resistance Source Impedance Analog Voltage Threshold Voltage T Note 1: See Section 30.0 “Electrical 2011 Microchip Technology Inc. PIC16(L)F1847 V DD 0. (1) LEAKAGE 0. Vss Specifications”. Preliminary To Comparator DS41453B-page 171 ...
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... Output updated on the falling edge of Timer1 clock source Comparator output to Timer1 and I/O pin is asynchronous DS41453B-page 172 R/W-0/0 U-0 R/W-1/1 CxPOL CxSP — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 CxHYS CxSYNC bit 0 2011 Microchip Technology Inc. ...
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... Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 MC2OUT: Mirror Copy of C2OUT bit bit 0 MC1OUT: Mirror Copy of C1OUT bit 2011 Microchip Technology Inc. R/W-0/0 U-0 CxPCH<1:0> — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
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... ANSA0 123 C1HYS C1SYNC 172 C1NCH<1:0> 173 C2HYS C2SYNC 173 C2NCH<1:0> 173 MC2OUT MC1OUT 173 — DACNSS 157 157 ADFVR<1:0> 136 INTF IOCF 89 LATA1 LATA0 122 — CCP2IE 91 — CCP2IF 95 RA1 RA0 122 TRISA1 TRISA0 122 2011 Microchip Technology Inc. ...
Page 175
... From CPSCLK 1 TMR0SE TMR0CS T0XCS 2011 Microchip Technology Inc. PIC16(L)F1847 20.1.2 8-BIT COUNTER MODE In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin or the Capacitive Sensing Oscillator (CPSCLK) signal. 8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION_REG register to ‘ ...
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... Section 30.0 “Electrical Specifications”. 20.1.6 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode. DS41453B-page 176 Preliminary 2011 Microchip Technology Inc. ...
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... Timer0 Module Register TRISA TRISA7 TRISA6 Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the Timer0 module. * Page provides register information. 2011 Microchip Technology Inc. R/W-1/1 R/W-1/1 R/W-1/1 TMR0SE PSA U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
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... PIC16(L)F1847 NOTES: DS41453B-page 178 Preliminary 2011 Microchip Technology Inc. ...
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... T1CKI Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. 2011 Microchip Technology Inc. • Gate Toggle Mode • Gate Single-pulse Mode • Gate Value Status • Gate Event Interrupt Figure 21 block diagram of the Timer1 module ...
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... T1CKI is high then Timer1 is enabled (TMR1ON=1) when T1CKI is low. T1OSCEN System Clock (F ) OSC x Instruction Clock (F OSC x Capacitive Sensing Oscillator x External Clocking on T1CKI Pin 0 Osc.Circuit On T1OSI/T1OSO Pins 1 Preliminary internal clock source is selected, the system clock or they can run Clock Source /4) 2011 Microchip Technology Inc. ...
Page 181
... A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair. 2011 Microchip Technology Inc. PIC16(L)F1847 21.6 Timer1 Gate Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 Gate circuitry ...
Page 182
... TMR1GIF flag bit in the PIR1 register will be set. If the TMR1GIE bit in the PIE1 register is set, then an interrupt will be recognized. The TMR1GIF flag bit operates even when the Timer1 Gate is not enabled (TMR1GE bit is cleared). Preliminary Example 21-5 for timing Figure 21-6 for 2011 Microchip Technology Inc. ...
Page 183
... T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. 2011 Microchip Technology Inc. PIC16(L)F1847 21.9 ECCP/CCP Capture/Compare Time Base The CCP modules use the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode ...
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... PIC16(L)F1847 FIGURE 21-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL Timer1 N FIGURE 21-4: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL Timer1 DS41453B-page 184 Preliminary 2011 Microchip Technology Inc ...
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... TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF 2011 Microchip Technology Inc. PIC16(L)F1847 Cleared by hardware on falling edge of T1GVAL Set by hardware on falling edge of T1GVAL Preliminary Cleared by software DS41453B-page 185 ...
Page 186
... TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF DS41453B-page 186 Set by hardware on falling edge of T1GVAL Preliminary 2011 Microchip Technology Inc. Cleared by hardware on falling edge of T1GVAL Cleared by software ...
Page 187
... This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 1X. bit 1 Unimplemented: Read as ‘0’ bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Clears Timer1 Gate flip-flop 2011 Microchip Technology Inc. PIC16(L)F1847 R/W-0/u R/W-0/u R/W-0/u T1OSCEN T1SYNC U = Unimplemented bit, read as ‘0’ ...
Page 188
... Comparator 1 optionally synchronized output (SYNCC1OUT Comparator 2 optionally synchronized output (SYNCC2OUT) DS41453B-page 188 R/W-0/u R/W/HC-0/u R-x/x T1GSPM T1GGO/ T1GVAL DONE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets HC = Bit is cleared by hardware Preliminary R/W-0/u R/W-0/u T1GSS<1:0> bit 0 2011 Microchip Technology Inc. ...
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... TRISB TRISB7 TRISB6 TMR1CS<1:0> T1CON TMR1GE T1GPOL T1GCON Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. * Page provides register information. 2011 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 ANSB5 ANSB4 ANSB3 ANSB2 DC1B<1:0> CCP1M<3:0> ...
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... PIC16(L)F1847 NOTES: DS41453B-page 190 Preliminary 2011 Microchip Technology Inc. ...
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... Optional use as the shift clock for the MSSPx modules (Timer2 only) See Figure 22-1 for a block diagram of Timer2/4/6. FIGURE 22-1: TIMER2/4/6 BLOCK DIAGRAM Prescaler F /4 OSC 1:1, 1:4, 1:16, 1:64 2 TxCKPS<1:0> 2011 Microchip Technology Inc. PIC16(L)F1847 TMRx Output Reset TMRx Postscaler Comparator 1 PRx TxOUTPS<3:0> Preliminary ...
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... Timer2/4/6 Operation During Sleep The Timer2/4/6 timers cannot be operated while the the output processor is in Sleep mode. The contents of the TMRx and PRx registers will remain unchanged while the processor is in Sleep mode. the 4-bit Preliminary Section 25.0 2011 Microchip Technology Inc. ...
Page 193
... TMRxON: Timerx On bit 1 = Timerx Timerx is off bit 1-0 TxCKPS<1:0>: Timer2-type Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler Prescaler is 64 2011 Microchip Technology Inc. PIC16(L)F1847 R/W-0/0 R/W-0/0 R/W-0/0 TMRxON U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary ...
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... T2OUTPS<3:0> TMR2ON T4OUTPS<3:0> TMR4ON T6OUTPS<3:0> TMR6ON Preliminary Register Bit 1 Bit 0 on Page INTF IOCF 89 TMR2IE TMR1IE 90 TMR2IF TMR1IF 94 — TMR4IE — 92 — TMR4IF — 96 191* 191* 191* T2CKPS<1:0> 193 T4CKPS<1:0> 193 T6CKPS<1:0> 193 191* 191* 191* 2011 Microchip Technology Inc. ...
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... Reserved * No Channel * Selected 1111 2011 Microchip Technology Inc. Using this method, the DSM can generate the following types of Key Modulation schemes: • Frequency-Shift Keying (FSK) • Phase-Shift Keying (PSK) • On-Off Keying (OOK) Additionally, the following features are provided within the DSM module: • ...
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... MDCHSYNC bit in the MDCARH register. Synchroniza- tion for the carrier low signal can be enabled by setting the MDCLSYNC bit in the MDCARL register. Figure 23-1 through Figure 23-5 of using various synchronization methods. Preliminary 2011 Microchip Technology Inc. show timing diagrams ...
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... Active Carrier State FIGURE 23-3: CARRIER HIGH SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 0) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 1 MDCLSYNC = 0 CARH Active Carrier State 2011 Microchip Technology Inc. PIC16(L)F1847 CARL CARH CARH CARL both Preliminary CARL both CARL DS41453B-page 197 ...
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... Active Carrier CARH State FIGURE 23-5: FULL SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 1) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) Falling edges used to sync MDCHSYNC = 1 MDCLSYNC = 1 Active Carrier CARH State DS41453B-page 198 CARL CARH CARL CARH Preliminary 2011 Microchip Technology Inc. CARL CARL ...
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... Effects of a Reset Upon any device Reset, the Data Signal Modulator module is disabled. The user’s firmware is responsible for initializing the module before enabling the output. The registers are reset to their default values. 2011 Microchip Technology Inc. PIC16(L)F1847 Preliminary DS41453B-page 199 ...
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... MDBIT must be selected as the modulation source in the MDSRC register for this operation. 2: DS41453B-page 200 R/W-0/0 R-0/0 U-0 MDOPOL MDOUT — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary U-0 R/W-0/0 — MDBIT bit 0 (2) 2011 Microchip Technology Inc. ...