PIC18LF13K22-E/SO Microchip Technology, PIC18LF13K22-E/SO Datasheet - Page 201

• Manufacturer Part Number: PIC18LF13K22-E/SO
• Description: 8KB Flash, 256bytes RAM, 256bytes EEPROM, 16MIPS, NanoWatt XLP 20 SOIC .300in TU
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF13K22-E/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART, I2C, SPI
• Maximum Clock Frequency: 32 KHz
• Number Of Programmable I/os: 18
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• A/d Bit Size: 10 bit
• A/d Channels Available: 12
• Height: 2.05 mm
• Length: 12.8 mm
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.8 V, 2.7 V
• Width: 7.5 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 15-7:
15.4.1.6
Data is received at the RX/DT pin. The RX/DT pin
output driver must be disabled by setting the
corresponding TRIS bits when the EUSART is
configured for synchronous master receive operation.
In Synchronous mode, reception is enabled by setting
either the Single Receive Enable bit (SREN of the
RCSTA register) or the Continuous Receive Enable bit
(CREN of the RCSTA register).
When SREN is set and CREN is clear, only as many
clock cycles are generated as there are data bits in a
single character. The SREN bit is automatically cleared
at the completion of one character. When CREN is set,
clocks are continuously generated until CREN is
cleared. If CREN is cleared in the middle of a character
the CK clock stops immediately and the partial charac-
ter is discarded. If SREN and CREN are both set, then
SREN is cleared at the completion of the first character
and CREN takes precedence.
To initiate reception, set either SREN or CREN. Data is
sampled at the RX/DT pin on the trailing edge of the
TX/CK clock pin and is shifted into the Receive Shift
Register (RSR). When a complete character is
received into the RSR, the RCIF bit is set and the
character is automatically transferred to the two
character receive FIFO. The Least Significant eight bits
of the top character in the receive FIFO are available in
RCREG. The RCIF bit remains set as long as there are
unread characters in the receive FIFO.
 2010 Microchip Technology Inc.
BAUDCON
INTCON
IPR1
PIE1
PIR1
RCSTA
SPBRG
SPBRGH
TRISC
TXREG
TXSTA
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
Name
Synchronous Master Reception
EUSART Baud Rate Generator Register, Low Byte
EUSART Baud Rate Generator Register, High Byte
EUSART Transmit Register
GIE/GIEH PEIE/GIEL TMR0IE
ABDOVF
TRISC7
CSRC
SPEN
Bit 7
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
—
—
—
TRISC6
RCIDL
ADIP
ADIE
ADIF
Bit 6
RX9
TX9
TRISC5
DTRXP
SREN
TXEN
RCIP
RCIE
RCIF
Bit 5
Preliminary
TRISC4
CKTXP
INT0IE
CREN
SYNC
TXIP
TXIE
TXIF
Bit 4
PIC18F1XK22/LF1XK22
ADDEN
TRISC3
SENDB
BRG16
RABIE
SSPIP
SSPIE
SSPIF
15.4.1.7
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device configured
as a slave receives the clock on the TX/CK line. The
TX/CK pin output driver must be disabled by setting the
associated TRIS bit when the device is configured for
synchronous slave transmit or receive operation. Serial
data bits change on the leading edge to ensure they are
valid at the trailing edge of each clock. One data bit is
transferred for each clock cycle. Only as many clock
cycles should be received as there are data bits.
15.4.1.8
The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before RCREG is read to access
the FIFO. When this happens the OERR bit of the
RCSTA register is set. Previous data in the FIFO will
not be overwritten. The two characters in the FIFO
buffer can be read, however, no additional characters
will be received until the error is cleared. The OERR bit
can only be cleared by clearing the overrun condition.
If the overrun error occurred when the SREN bit is set
and CREN is clear then the error is cleared by reading
RCREG. If the overrun occurred when the CREN bit is
set then the error condition is cleared by either clearing
the CREN bit of the RCSTA register or by clearing the
SPEN bit which resets the EUSART.
Bit 3
TMR0IF
CCP1IP
CCP1IE
CCP1IF
TRISC2
BRGH
FERR
Bit 2
—
Slave Clock
Receive Overrun Error
TMR2IP
TMR2IE
TMR2IF
TRISC1
INT0IF
OERR
TRMT
WUE
Bit 1
TMR1IP
TMR1IE
TMR1IF
TRISC0
ABDEN
RABIF
RX9D
TX9D
Bit 0
DS41365D-page 201
on page
Values
Reset
259
257
260
260
260
259
259
259
260
259
259