PIC18LF13K22-E/SO Microchip Technology, PIC18LF13K22-E/SO Datasheet - Page 253

• Manufacturer Part Number: PIC18LF13K22-E/SO
• Description: 8KB Flash, 256bytes RAM, 256bytes EEPROM, 16MIPS, NanoWatt XLP 20 SOIC .300in TU
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF13K22-E/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART, I2C, SPI
• Maximum Clock Frequency: 32 KHz
• Number Of Programmable I/os: 18
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• A/d Bit Size: 10 bit
• A/d Channels Available: 12
• Height: 2.05 mm
• Length: 12.8 mm
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.8 V, 2.7 V
• Width: 7.5 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.5
PIC18F1XK22/LF1XK22 devices incorporate three
separate on-chip timers that help regulate the
Power-on Reset process. Their main function is to
ensure that the device clock is stable before code is
executed. These timers are:
• Power-up Timer (PWRT)
• Oscillator Start-up Timer (OST)
• PLL Lock Time-out
21.5.1
The
PIC18F1XK22/LF1XK22 devices is an 11-bit counter
which uses the LFINTOSC source as the clock input.
This
2048 x 32 s = 65.6 ms. While the PWRT is counting,
the device is held in Reset.
The power-up time delay depends on the LFINTOSC
clock and will vary from chip-to-chip due to temperature
and process variation. See Section 25.0 “Electrical
Specifications” for details.
The PWRT is enabled by clearing the PWRTEN
Configuration bit.
21.5.2
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal
oscillator or resonator has started and stabilized.
TABLE 21-2:
 2010 Microchip Technology Inc.
HSPLL
HS, XT, LP
EC, ECIO
RC, RCIO
INTIO1, INTIO2
Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
Configuration
yields
2: 2 ms is the nominal time required for the PLL to lock.
Oscillator
Device Reset Timers
Power-up
POWER-UP TIMER (PWRT)
OSCILLATOR START-UP TIMER
(OST)
an
TIME-OUT IN VARIOUS SITUATIONS
approximate
Timer
66 ms
66 ms
(1)
PWRTEN = 0
+ 1024 T
time
(1)
66 ms
66 ms
66 ms
(PWRT)
+ 1024 T
interval
Power-up
OSC
(1)
(1)
(1)
+ 2 ms
OSC
Preliminary
of
of
(2)
(2)
and Brown-out
PIC18F1XK22/LF1XK22
The OST time-out is invoked only for XT, LP, HS and
HSPLL modes and only on Power-on Reset, or on exit
from all power-managed modes that stop the external
oscillator.
21.5.3
With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly
different from other oscillator modes. A separate timer
is used to provide a fixed time-out that is sufficient for
the PLL to lock to the main oscillator frequency. This
PLL lock time-out (T
oscillator start-up time-out.
21.5.4
On power-up, the time-out sequence is as follows:
1.
2.
The total time-out will vary based on oscillator
configuration and the status of the PWRT. Figure 21-3,
Figure 21-4, Figure 21-5, Figure 21-6 and Figure 21-7
all depict time-out sequences on power-up, with the
Power-up Timer enabled and the device operating in
HS Oscillator mode. Figures 21-3 through 21-6 also
apply to devices operating in XT or LP modes. For
devices in RC mode and with the PWRT disabled, on
the other hand, there will be no time-out at all.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, all time-outs will expire, after
which, bringing MCLR high will allow program
execution to begin immediately (Figure 21-5). This is
useful for testing purposes or to synchronize more than
one PIC18F1XK22/LF1XK22 device operating in
parallel.
1024 T
PWRTEN = 1
After the POR pulse has cleared, PWRT time-out
is invoked (if enabled).
Then, the OST is activated.
1024 T
OSC
—
—
—
PLL LOCK TIME-OUT
TIME-OUT SEQUENCE
+ 2 ms
OSC
(2)
PLL
) is typically 2ms and follows the
Power-Managed Mode
1024 T
DS41365D-page 253
1024 T
Exit from
OSC
—
—
—
+ 2 ms
OSC
(2)