PIC18LF13K22-E/SO Microchip Technology, PIC18LF13K22-E/SO Datasheet
PIC18LF13K22-E/SO
Specifications of PIC18LF13K22-E/SO
Related parts for PIC18LF13K22-E/SO
PIC18LF13K22-E/SO Summary of contents
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... Flash Memory Programming Specification 1.0 DEVICE OVERVIEW This document includes the specifications for the following devices: • PIC18F13K22 • PIC18LF13K22 • PIC18F14K22 • PIC18LF14K22 2.0 PROGRAMMING OVERVIEW The PIC18F1XK22/LF1XK22 devices programmed using either the high-voltage In-Circuit Serial Programming™ (ICSP™) method or the low- voltage ICSP method. Both methods can be done with the device in the users’ ...
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... All power supply (V ) and ground (V DD DS41357B-page 2 During Programming Pin Description P Programming Enable P Power Supply P Ground I Low-Voltage ICSP™ input when LVP Configuration bit equals ‘1’ I Serial Clock I/O Serial Data ) pins must be connected. SS Advance Information (1) © 2009 Microchip Technology Inc. ...
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... FIGURE 2-1: 20-PIN PDIP, SSOP AND SOIC PIN DIAGRAM FOR PIC18F1XK22/LF1XK22 20-pin PDIP, SSOP, SOIC (300 MIL) RA5/OSC1/CLKIN/T13CKI RA4/AN3/OSC2/CLKOUT RA3/MCLR/V RC5/CCP1/P1A RC4/C2OUT/P1B/SRQ RC3/AN7/C12IN3-/P1C/PGM RC6/AN8/SS RC7/AN9/SDO RB7/TX/CK 20-Pin QFN 4x4 RA3/MCLR/V RC5/CCP1/P1A RC4/C2OUT/P1B/SRQ RC3/AN7/C12IN3-/P1C/PGM RC6/AN8/SS © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 ...
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... Boot Block (2) Boot Block Block 0 Block 0 Block 1 Block 1 Unimplemented Unimplemented Read ‘0’s Read ‘0’s Advance Information Program Flash Size (Bytes) 000000h-001FFFh (8K) 000000h-003FFFh (16K) Address Range 000000h 0007FFh 000800h 000FFFh 001000h 001FFFh 002000h 003FFFh 004000h 01FFFFh © 2009 Microchip Technology Inc. ...
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... Unimplemented Read as ‘0’ 200000h Configuration and ID Space 3FFFFFh Note 1: Sizes of memory areas are not to scale. 2: Boot Block size is determined by the BBSIZ bit in the CONFIG4L register. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 MEMORY SIZE/DEVICE 8 Kbytes (PIC18F13K22) BBSIZ = 1 BBSIZ = 0 (2) Boot Block ...
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... ID Location 6 200005h ID Location 7 200006h ID Location 8 200007h CONFIG1H 300001h CONFIG2L 300002h CONFIG2H 300003h 300004h CONFIG3H 300005h CONFIG4L 300006h 300007h CONFIG5L 300008h CONFIG5H 300009h CONFIG6L 30000Ah CONFIG6H 30000Bh CONFIG7L 30000Ch CONFIG7H 30000Dh Device ID1 3FFFFEh Device ID2 3FFFFFh © 2009 Microchip Technology Inc. ...
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... Verify IDs Verify Data Program Configuration Bits Verify Configuration Bits Done © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 3.2 Entering and Exiting High-Voltage ICSP Program/Verify Mode As shown in Figure 3-6, the High-Voltage ICSP Program/Verify mode is entered by holding PGC and PGD low and then raising MCLR/V (high voltage) ...
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... ENTERING LOW-VOLTAGE PROGRAM/VERIFY MODE P15 P12 V IH MCLR/V /RA3 PGM PGD PGC PGD = Input DS41357B-page 8 FIGURE 3-9: MCLR/V /RA3 PGM PGD PGC is ‘1’ (see /RA3 Advance Information EXITING LOW-VOLTAGE PROGRAM/VERIFY MODE P16 P18 PGD = Input © 2009 Microchip Technology Inc. ...
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... Table Read Table Read, post-increment Table Read, post-decrement Table Read, pre-increment Table Write Table Write, post-increment by 2 Table Write, start programming, post-increment by 2 Table Write, start programming © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 4-Bit Command 0000 0010 1000 1001 1010 1011 ...
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... Core Instruction Command Payload 1101 3C 40 Table Write, post-increment by 2 FIGURE 3-10: TABLE WRITE, POST-INCREMENT TIMING DIAGRAM (1101) P2 P2A P2B PGC PGD 4-bit Command DS41357B-page 16-bit Data Payload PGD = Input Advance Information P5A Fetch Next 4-bit Command © 2009 Microchip Technology Inc. ...
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... P11). During this time, PGC may continue to toggle but PGD must be held low. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 The code sequence to erase the entire device is shown in Table 4-2 and the flowchart is shown in Figure 4-1. ...
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... Section 4.1.3 “ICSP Row Erase”. The address argument used should be 0x200000. A row erase of the User ID locations is required when V below the Bulk Erase threshold. Advance Information P10 P11 16-bit Erase Time Data Payload is DD © 2009 Microchip Technology Inc. ...
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... Step 6: Repeat step 3 with Address Pointer incremented by 64 until all rows are erased. Step 7: Disable writes 0000 Note 1: See Figure 5-4 for details on shift out data timing. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Core Instruction BSF EECON1, EEPGD BCF EECON1, CFGS ...
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... PIC18F1XK22/LF1XK22 FIGURE 4-3: SINGLE ROW ERASE PROGRAM FLASH FLOW Addr = Addr + 64 DS41357B-page 14 Start Addr = 0 Configure Device for Row Erases Perform Erase Sequence No WR Bit Clear? Yes All No Rows done? Yes Done Advance Information © 2009 Microchip Technology Inc. ...
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... To continue writing data, repeat steps 2 through 4, where the Address Pointer is incremented each iteration of the loop. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 After PGC is brought low, the programming sequence is terminated. PGC must be held low for the time specified by parameter P10 to allow high-voltage discharge of the memory array ...
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... Yes Start Write Sequence and Hold PGC High until Done and Wait P9 Hold PGC Low for Time P10 All No locations done? Yes Done P5A 4-bit Command PGD = Input Advance Information P10 ( 16-bit Programming Time Data Payload © 2009 Microchip Technology Inc. ...
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... Table 4-4) at each iteration of the loop. The write cycle must be repeated enough times to completely rewrite the contents of the erase buffer. Step 8: Disable writes 0000 © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 The appropriate number of bytes required for the erase buffer must be read out of program Flash (as described in Section 5.2 “Verify Program Flash and ID Loca- tions” ...
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... PROGRAM DATA FLOW Start Set Address Set Data Enable Write Start Write Sequence No WR bit clear? Yes No done? Yes Done P10 1 2 P11A n n 16-bit Data Payload (see below P5A Shift Out Data (see Figure 4-4) PGD = Output © 2009 Microchip Technology Inc. ...
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... Step 7: Hold PGC low for time P10. Step 8: Disable writes 0000 Repeat steps 2 through 8 to write more data. Note 1: See Figure 5-4 for details on shift out data timing. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Core Instruction BCF EECON1, EEPGD BCF EECON1, CFGS MOVLW <Addr> ...
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... Write 2 bytes and post-increment address by 2. Write 2 bytes and post-increment address by 2. Write 2 bytes and post-increment address by 2. Write 2 bytes and start programming. NOP - hold PGC high for time P9 and low for time P10. Advance Information © 2009 Microchip Technology Inc. ...
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... Address Program LSB Delay P9 and P10 Time for Write Done © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 4.6 Configuration Bits Programming Unlike program Flash, the Configuration bits are programmed a byte at a time. The Table Write, Begin Programming 4-bit command (‘1111’) is used, but only 8 bits of the following 16-bit payload will be written ...
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... ID and Configuration registers. Core Instruction MOVLW Addr[21:16] MOVWF TBLPTRU MOVLW <Addr[15:8]> MOVWF TBLPTRH MOVLW <Addr[7:0]> MOVWF TBLPTRL TBLRD *+ P14 3 LSb 1 2 Shift Data Out PGD = Output Advance Information P5A (Note MSb Fetch Next 4-bit Command PGD = Input © 2009 Microchip Technology Inc. ...
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... Yes All No program Flash verified? Yes © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 The Table Pointer must be manually set to 200000h (base address of the ID locations) once the program Flash has been verified. The post-increment feature of the table read 4-bit command can not be used to increment the Table Pointer beyond the program Flash space ...
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... BCF EECON1, CFGS MOVLW <Addr> MOVWF EEADR BSF EECON1, RD MOVF EEDATA MOVWF TABLAT NOP (1) Shift Out Data Advance Information READ DATA EEPROM FLOW Start Set Address Read Byte Move to TABLAT Shift Out Data done? Yes Done © 2009 Microchip Technology Inc. ...
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... PGD via the 4-bit command, ‘0010’ (TABLAT register). The result may then be immediately compared to the appropriate data in the programmer’s memory for verification. Refer to Section 5.4 “Read Data EEPROM Memory” for implementation details of reading data EEPROM. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 ...
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... STVREN 10-- 01-1 — CP1 CP0 ---- --11 — — — 11-- ---- — WRT1 WRT0 ---- --11 — — — 111- ---- — EBTR1 EBTR0 ---- --11 — — — -1-- ---- REV1 REV0 See Table 6-2 DEV4 DEV3 See Table 6-2 © 2009 Microchip Technology Inc. ...
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... TABLE 6-2: DEVICE ID VALUE Device PIC18LF13K22 PIC18LF14K22 PIC18F13K22 PIC18F14K22 Note: The ‘x’s in DEVID1 contain the device revision code. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Device ID Value DEVID2 4Fh 4Fh 4Fh 4Fh Advance Information DEVID1 100x xxxx 011x xxxx 010x xxxx ...
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... Brown-out Reset enabled in hardware only (SBOREN is disabled Brown-out Reset enabled in hardware only and disabled in Sleep mode SBOREN is disabled Brown-out Reset enabled and controlled by software (SBOREN is enabled Brown-out Reset disabled in hardware and software Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled Advance Information © 2009 Microchip Technology Inc. ...
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... CONFIG4L LVP CONFIG4L STVREN CONFIG4L CP1 CONFIG5L CP0 CONFIG5L CPD CONFIG5H . © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Description Watchdog Timer Postscaler Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 ...
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... These bits are used with the DEV<2:0> bits in the DEVID1 register to identify part number. Device ID bits These bits are used with the DEV<10:3> bits in the DEVID2 register to identify part number. Revision ID bits These bits are used to indicate the revision of the device. Advance Information © 2009 Microchip Technology Inc. ...
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... EEPROM information must be included. An option to not include the data EEPROM information may be provided. When embedding data EEPROM information in the hex file, it should start at address F00000h. Microchip Technology Inc. believes that this feature is important for the benefit of the end customer. 7.2 Checksum Computation The checksum is calculated by summing the following: • ...
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... CDh)+(CONFIG4H & 00h)+(CONFIG5L & 03h)+ (CONFIG5H & C0h)+(CONFIG6L & 03h)+(CONFIG6H & E0h)+ PIC18F13K22/ (CONFIG7L & 03h)+(CONFIG7H & 40h)+SUM_ID PIC18LF13K22 Boot/ SUM[1000:1FFF]+ Block 0 (CONFIG1L & 00h)+(CONFIG1H & FFh)+(CONFIG2L & 1Fh)+ (CONFIG2H & ...
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... T CY PWRT only) + 1.5 μs (for EC mode only) where T and T is the oscillator period. For specific values, refer to the Electrical Characteristics section of the device OSC data sheet for the particular device. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Min. Max 1. ...
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... Units Conditions μs — μs — PIC18F1XK22 Only. Refer to Figure 2.1.1. — ns μs — PIC18F1XK22 Only. Refer to Figure 2.1.1. — ns μs — — — μs — ; this can cause spurious program is the Power-up Timer period PWRT © 2009 Microchip Technology Inc. ...
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... PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08- Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 03/26/09 © 2009 Microchip Technology Inc. ...