PIC18LF13K22-E/SS Microchip Technology, PIC18LF13K22-E/SS Datasheet - Page 262

• Manufacturer Part Number: PIC18LF13K22-E/SS
• Description: 8KB Flash, 256bytes RAM, 256bytes EEPROM, 16MIPS, NanoWatt XLP 20 SSOP .209in TU
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF13K22-E/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SSOP
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART, I2C, SPI
• Maximum Clock Frequency: 32 KHz
• Number Of Programmable I/os: 18
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F1XK22/LF1XK22
22.1
The Configuration bits can be programmed (read as
‘0’) or left unprogrammed (read as ‘1’) to select various
device configurations. These bits are mapped starting
at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h-3FFFFFh), which
can only be accessed using table reads and table writes.
Programming the Configuration registers is done in a
manner similar to programming the Flash memory. The
WR bit in the EECON1 register starts a self-timed write
to the Configuration register. In normal operation mode,
a TBLWT instruction with the TBLPTR pointing to the
Configuration register sets up the address and the data
for the Configuration register write. Setting the WR bit
starts a long write to the Configuration register. The
Configuration registers are written a byte at a time. To
write or erase a configuration cell, a TBLWT instruction
can write a ‘1’ or a ‘0’ into the cell. For additional details
on Flash programming, refer to Section 4.5 “Writing
to Flash Program Memory”.
TABLE 22-1:
DS41365D-page 262
300001h CONFIG1H
300002h CONFIG2L
300003h CONFIG2H
300005h CONFIG3H MCLRE
300006h CONFIG4L
300008h CONFIG5L
300009h CONFIG5H
30000Ah CONFIG6L
30000Bh CONFIG6H
30000Ch CONFIG7L
30000Dh CONFIG7H
3FFFFEh DEVID1
3FFFFFh DEVID2
Legend:
Note 1:
File Name
Configuration Bits
x = unknown, u = unchanged, – = unimplemented, q = value depends on condition.
Shaded cells are unimplemented, read as ‘0’
See Register 22-12 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user.
(1)
(1)
CONFIGURATION BITS AND DEVICE IDs
BKBUG ENHCPU
DEV10
WRTD
DEV2
IESO
Bit 7
CPD
—
—
—
—
—
—
FCMEN
EBTRB
WRTB
DEV1
DEV9
Bit 6
CPB
—
—
—
—
—
—
PCLKEN
WRTC
DEV0
DEV8
Bit 5
—
—
—
—
—
—
—
—
—
Preliminary
WDTPS3
PLL_EN
BORV1
REV4
DEV7
Bit 4
—
—
—
—
—
—
—
—
WDTPS2
HFOFST
BORV0
FOSC3
BBSIZ
REV3
DEV6
Bit 3
—
—
—
—
—
—
WDTPS1 WDTPS0
BOREN1 BOREN0 PWRTEN
FOSC2
REV2
DEV5
Bit 2
LVP
—
—
—
—
—
—
—
FOSC1
EBTR1
WRT1
REV1
DEV4
Bit 1
CP1
—
—
—
—
—
 2010 Microchip Technology Inc.
STVREN
WDTEN
FOSC0
EBTR0
WRT0
REV0
DEV3
Bit 0
CP0
—
—
—
—
Unprogrammed
0010 0111
---1 1111
---1 1111
1--- 1---
-0-- 01-1
---- --11
11-- ----
---- --11
111- ----
---- --11
-1-- ----
qqqq qqqq
0000 1100
Default/
Value
(1)