PIC24FV16KA304T-I/ML Microchip Technology, PIC24FV16KA304T-I/ML Datasheet - Page 249

• Manufacturer Part Number: PIC24FV16KA304T-I/ML
• Description: 16KB Flash, 2KB RAM, 512B EEPROM, 16 MIPS, 12-bit ADC, CTMU, 5V 44 QFN 8x8x0.9mm
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FV16KA304T-I/ML

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 16KB (5.5K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-VQFN Exposed Pad
• Processor Series: PIC24FV
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The WDT, prescaler and postscaler are reset:
• On any device Reset
• On the completion of a clock switch, whether
• When a PWRSAV instruction is executed
• When the device exits Sleep or Idle mode to
• By a CLRWDT instruction during normal execution
If the WDT is enabled in hardware (FWDTEN<1:0> = 11),
it will continue to run during Sleep or Idle modes. When
the WDT time-out occurs, the device will wake and code
execution will continue from where the PWRSAV
instruction was executed. The corresponding SLEEP or
IDLE bits (RCON<3:2>) will need to be cleared in
software after the device wakes up.
The WDT Flag bit, WDTO (RCON<4>), is not
automatically cleared following a WDT time-out. To
detect subsequent WDT events, the flag must be
cleared in software.
FIGURE 26-2:
 2011 Microchip Technology Inc.
invoked by software (i.e., setting the OSWEN bit
after changing the NOSC bits) or by hardware
(i.e., Fail-Safe Clock Monitor)
(i.e., Sleep or Idle mode is entered)
resume normal operation
Note:
Sleep or Idle Mode
New Clock Source
All Device Resets
CLRWDT Instr.
PWRSAV Instr.
Exit Sleep or
Transition to
LPRC Input
Idle Mode
SWDTEN
FWDTEN
The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
WDT BLOCK DIAGRAM
31 kHz
(5-Bit/7-Bit)
Prescaler
FWPSA
1 ms/4 ms
LPRC Control
PIC24FV32KA304 FAMILY
Counter
WDT
26.3.1
The Watchdog Timer has an optional Fixed Window
mode of operation. In this Windowed mode, CLRWDT
instructions can only reset the WDT during the last 1/4
of the programmed WDT period. A CLRWDT instruction
executed before that window causes a WDT Reset,
similar to a WDT time-out.
Windowed WDT mode is enabled by programming the
Configuration bit, WINDIS (FWDT<6>), to ‘0’.
26.3.2
The WDT is enabled or disabled by the FWDTEN<1:0>
Configuration bits. When both the FWDTEN<1:0> Con-
figuration bits are set, the WDT is always enabled.
The WDT can be optionally controlled in software when
the FWDTEN<1:0> Configuration bits have been pro-
grammed to ‘10’. The WDT is enabled in software by
setting the SWDTEN control bit (RCON<5>). The
SWDTEN control bit is cleared on any device Reset.
The software WDT option allows the user to enable the
WDT for critical code segments, and disable the WDT
during non-critical segments, for maximum power sav-
ings. When the FWTEN<1:0> bits are set to ‘01’, the
WDT is enabled only in Run and Idle modes, and is dis-
abled in Sleep. Software control of the WDT SWDTEN
bit (RCON<5>) is disabled with this setting.
1:1 to 1:32.768
WDTPS<3:0>
Postscaler
WINDOWED OPERATION
CONTROL REGISTER
DS39995B-page 249
Wake from Sleep
WDT Overflow
Reset