PIC32MX210F016B-I/SO Microchip Technology, PIC32MX210F016B-I/SO Datasheet - Page 110

• Manufacturer Part Number: PIC32MX210F016B-I/SO
• Description: PIC32, 16KB Flash, 4KB RAM, 40 MHz, USB, CTMU, 4 DMA 28 SOIC .300in TUBE
• Manufacturer: Microchip Technology

PIC32MX1XX/2XX
REGISTER 9-5:
REGISTER 9-6:
DS61168D-page 110
Legend:
R = Readable bit
-n = Value at POR
bit 31-0 DCRCDATA<31:0>: CRC Data Register bits
Legend:
R = Readable bit
-n = Value at POR
bit 31-0 DCRCXOR<31:0>: CRC XOR Register bits
Range
Range
31:24
23:16
31:24
23:16
15:8
15:8
Bit
7:0
7:0
Bit
Writing to this register will seed the CRC generator. Reading from this register will return the current value of
the CRC. Bits greater than PLEN will return ‘0’ on any read.
When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):
Only the lower 16 bits contain IP header checksum information. The upper 16 bits are always ‘0’. Data written
to this register is converted and read back in 1’s complement form (i.e., current IP header checksum value).
When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):
Bits greater than PLEN will return ‘0’ on any read.
When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):
This register is unused.
When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):
1 = Enable the XOR input to the Shift register
0 = Disable the XOR input to the Shift register; data is shifted in directly from the previous stage in
31/23/15/7
31/23/15/7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
the register
Bit
Bit
DCRCDATA: DMA CRC DATA REGISTER
DCRCXOR: DMA CRCXOR ENABLE REGISTER
30/22/14/6
30/22/14/6
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit
Bit
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
29/21/13/5
29/21/13/5
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit
Bit
Preliminary
28/20/12/4
28/20/12/4
DCRCDATA<31:24>
DCRCDATA<23:16>
DCRCXOR<31:24>
DCRCXOR<23:16>
DCRCDATA<15:8>
DCRCXOR<15:8>
DCRCDATA<7:0>
DCRCXOR<7:0>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit
Bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
27/19/11/3
27/19/11/3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit
Bit
(1,2,3)
26/18/10/2
26/18/10/2
R/W-0
R/W-0
R/W-0
R/W-0
© 2011-2012 Microchip Technology Inc.
R/W-0
R/W-0
R/W-0
R/W-0
Bit
Bit
x = Bit is unknown
x = Bit is unknown
25/17/9/1
25/17/9/1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit
Bit
24/16/8/0
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit
Bit