PIC32MX210F016B-I/SO Microchip Technology, PIC32MX210F016B-I/SO Datasheet - Page 165

• Manufacturer Part Number: PIC32MX210F016B-I/SO
• Description: PIC32, 16KB Flash, 4KB RAM, 40 MHz, USB, CTMU, 4 DMA 28 SOIC .300in TUBE
• Manufacturer: Microchip Technology

16.0
FIGURE 16-1:
© 2011-2012 Microchip Technology Inc.
Note 1: This data sheet summarizes the features
Note: Access SPIxTXB and SPIxRXB FIFOs via SPIxBUF register.
2: Some registers and associated bits
SERIAL PERIPHERAL
INTERFACE (SPI)
of the PIC32MX1XX/2XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 23. “Serial
Peripheral Interface (SPI)” (DS61106) in
the “PIC32 Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com/PIC32).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
SSx/F
SDOx
SCKx
SDIx
SYNC
SPI MODULE BLOCK DIAGRAM
Receive
Slave Select
Sync Control
and Frame
Read
SPIxRXB FIFO
bit 0
SPIxBUF
SPIxSR
SPIxTXB FIFO
Control
Clock
Control
Shift
Preliminary
in
Write
Transmit
Data Bus
Internal
Select
Edge
The SPI module is a synchronous serial interface that
is useful for communicating with external peripherals
and other microcontroller devices. These peripheral
devices may be Serial EEPROMs, Shift registers, dis-
play drivers, Analog-to-Digital Converters (ADC), etc.
The PIC32 SPI module is compatible with Motorola
SPI and SIOP interfaces.
Some of the key features of the SPI module are:
• Master and Slave modes support
• Four different clock formats
• Enhanced Framed SPI protocol support
• User-configurable 8-bit, 16-bit and 32-bit data width
• Separate SPI FIFO buffers for receive and transmit
• Programmable interrupt event on every 8-bit,
• Operation during CPU Sleep and Idle mode
• Audio Codec Support:
- FIFO buffers act as 4/8/16-level deep FIFOs
16-bit and 32-bit data transfer
- I
- Left-justified
- Right-justified
- PCM
based on 32/16/8-bit data width
2
S protocol
MSTEN
PIC32MX1XX/2XX
Baud Rate
Generator
FIFOs Share Address SPIxBUF
MCLKSEL
DS61168D-page 165
REFCLK
PBCLK
®