PIC32MX210F016B-I/SO Microchip Technology, PIC32MX210F016B-I/SO Datasheet - Page 188

• Manufacturer Part Number: PIC32MX210F016B-I/SO
• Description: PIC32, 16KB Flash, 4KB RAM, 40 MHz, USB, CTMU, 4 DMA 28 SOIC .300in TUBE
• Manufacturer: Microchip Technology

PIC32MX1XX/2XX
REGISTER 19-2:
DS61168D-page 188
Legend:
R = Readable bit
-n = Value at POR
bit 31-16 Unimplemented: Read as ‘0’
bit 15
bit 14-13 IRQM<1:0>: Interrupt Request Mode bits
bit 12-11 INCM<1:0>: Increment Mode bits
bit 10
bit 9-8
bit 7-6
Range
31:24
23:16
15:8
Note 1: Whenever WAITM<3:0> = 0000, WAITB and WAITE bits are ignored and forced to 1 T
7:0
Bit
2: Address bit A14 is not subject to auto-increment/decrement if configured as Chip Select CS1.
BUSY: Busy bit (Master mode only)
1 = Port is busy
0 = Port is not busy
11 = Reserved, do not use
10 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode)
01 = Interrupt generated at the end of the read/write cycle
00 = No Interrupt generated
11 = Slave mode read and write buffers auto-increment (PMMODE<1:0> = 00 only)
10 = Decrement ADDR<10:2> and ADDR<14> by 1 every read/write cycle
01 = Increment ADDR<10:2> and ADDR<14> by 1 every read/write cycle
00 = No increment or decrement of address
Unimplemented: Read as ‘0’
MODE<1:0>: Parallel Port Mode Select bits
11 = Master mode 1 (PMCS1, PMRD/PMWR, PMENB, PMA<x:0>, and PMD<7:0>)
10 = Master mode 2 (PMCS1, PMRD, PMWR, PMA<x:0>, and PMD<7:0>)
01 = Enhanced Slave mode, control signals (PMRD, PMWR, PMCS1, PMD<7:0>, and PMA<1:0>)
00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS1, and PMD<7:0>)
WAITB<1:0>: Data Setup to Read/Write Strobe Wait States bits
11 = Data wait of 4 T
10 = Data wait of 3 T
01 = Data wait of 2 T
00 = Data wait of 1 T
31/23/15/7
write operation; WAITB = 1 T
BUSY
R/W-0
Bit
U-0
U-0
R-0
—
—
WAITB<1:0>
or on a read or write operation when PMA<1:0> =11 (Addressable Slave mode only)
PMMODE: PARALLEL PORT MODE REGISTER
30/22/14/6
R/W-0
R/W-0
Bit
U-0
U-0
(1)
—
—
IRQM<1:0>
PB
PB
PB
PB
; multiplexed address phase of 4 T
; multiplexed address phase of 3 T
; multiplexed address phase of 2 T
; multiplexed address phase of 1 T
W = Writable bit
‘1’ = Bit is set
29/21/13/5
R/W-0
R/W-0
PBCLK
Bit
U-0
U-0
—
—
cycle, WAITE = 0 T
Preliminary
28/20/12/4
R/W-0
R/W-0
Bit
U-0
U-0
—
—
WAITM<3:0>
INCM<1:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
27/19/11/3
PBCLK
R/W-0
R/W-0
PB
PB
PB
PB
Bit
U-0
U-0
—
—
(1)
(default)
cycles for a read operation.
(1)
26/18/10/2
R/W-0
© 2011-2012 Microchip Technology Inc.
Bit
U-0
U-0
U-0
—
—
—
(2)
(2)
x = Bit is unknown
25/17/9/1
R/W-0
R/W-0
Bit
U-0
U-0
—
—
WAITE<1:0>
MODE<1:0>
PBCLK
24/16/8/0
cycle for a
R/W-0
R/W-0
Bit
U-0
U-0
(1)
—
—