PIC32MX210F016B-I/SO Microchip Technology, PIC32MX210F016B-I/SO Datasheet - Page 164

• Manufacturer Part Number: PIC32MX210F016B-I/SO
• Description: PIC32, 16KB Flash, 4KB RAM, 40 MHz, USB, CTMU, 4 DMA 28 SOIC .300in TUBE
• Manufacturer: Microchip Technology

PIC32MX1XX/2XX
REGISTER 15-1:
DS61168D-page 164
Legend:
R = Readable bit
-n = Value at POR
bit 31-16 Unimplemented: Read as ‘0’
bit 15
bit 14
bit 13
bit 12-6
bit 5
bit 4
bit 3
bit 2-0
Note 1:
Range
31:24
23:16
15:8
Bit
7:0
2:
ON: Output Compare Peripheral On bit
1 = Output Compare peripheral is enabled
0 = Output Compare peripheral is disabled
Unimplemented: Read as ‘0’
SIDL: Stop in Idle Mode bit
1 = Discontinue operation when CPU enters Idle mode
0 = Continue operation in Idle mode
Unimplemented: Read as ‘0’
OC32: 32-bit Compare Mode bit
1 = OCxR<31:0> and/or OCxRS<31:0> are used for comparisions to the 32-bit timer source
0 = OCxR<15:0> and OCxRS<15:0> are used for comparisons to the 16-bit timer source
OCFLT: PWM Fault Condition Status bit
1 = PWM Fault condition has occurred (cleared in HW only)
0 = No PWM Fault condition has occurred
OCTSEL: Output Compare Timer Select bit
1 = Timer3 is the clock source for this OCMP module
0 = Timer2 is the clock source for this OCMP module
OCM<2:0>: Output Compare Mode Select bits
111 = PWM mode on OCx; Fault pin enabled
110 = PWM mode on OCx; Fault pin disabled
101 = Initialize OCx pin low; generate continuous output pulses on OCx pin
100 = Initialize OCx pin low; generate single output pulse on OCx pin
011 = Compare event toggles OCx pin
010 = Initialize OCx pin high; compare event forces OCx pin low
001 = Initialize OCx pin low; compare event forces OCx pin high
000 = Output compare peripheral is disabled but continues to draw current
When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
This bit is only used when OCM<2:0> = ‘111’. It is read as ‘0’ in all other modes.
31/23/15/7
ON
R/W-0
Bit
U-0
U-0
U-0
—
—
—
(1)
OCxCON: OUTPUT COMPARE ‘x’ CONTROL REGISTER
30/22/14/6
Bit
U-0
U-0
U-0
U-0
—
—
—
—
W = Writable bit
‘1’ = Bit is set
29/21/13/5
OC32
R/W-0
SIDL
R/W-0
Bit
U-0
U-0
—
—
(1)
Preliminary
(2)
28/20/12/4
OCFLT
Bit
U-0
U-0
U-0
R-0
—
—
—
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
27/19/11/3
OCTSEL
R/W-0
Bit
U-0
U-0
U-0
—
—
—
26/18/10/2
© 2011-2012 Microchip Technology Inc.
R/W-0
Bit
U-0
U-0
U-0
—
—
—
OCM<2:0>
x = Bit is unknown
25/17/9/1
R/W-0
Bit
U-0
U-0
U-0
—
—
—
24/16/8/0
R/W-0
Bit
U-0
U-0
U-0
—
—
—