PIC32MX664F064HT-I/PT Microchip Technology, PIC32MX664F064HT-I/PT Datasheet - Page 130

• Manufacturer Part Number: PIC32MX664F064HT-I/PT
• Description: 64 PINS, 64KB Flash, 32KB RAM, 80 MHz, USB, Ethernet, 4 DMA 64 TQFP 10x10x1mm T/
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX664F064HT-I/PT

• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: Ethernet, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Processor Series: PIC32MX5x
• Core: MIPS32
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC32MX5XX/6XX/7XX
12.1
All port pins have three registers (TRIS, LAT and
PORT) that are directly associated with their operation.
TRIS is a Data Direction or Tri-State Control register
that determines whether a digital pin is an input or an
output. Setting a TRISx register bit = 1 configures the
corresponding I/O pin as an input; setting a TRISx
register bit = 0 configures the corresponding I/O pin as
an output. All port I/O pins are defined as inputs after a
device Reset. Certain I/O pins are shared with analog
peripherals and default to analog inputs after a device
Reset.
PORT is a register used to read the current state of the
signal applied to the port I/O pins. Writing to a PORTx
register performs a write to the port’s latch, LATx
register, latching the data to the port’s I/O pins.
LAT is a register used to write data to the port I/O pins.
The LATx Latch register holds the data written to either
the LATx or PORTx registers. Reading the LATx Latch
register
corresponding PORT or Latch register.
Not all port I/O pins are implemented on some devices,
therefore, the corresponding PORTx, LATx and TRISx
register bits will read as zeros.
12.1.1
Every I/O module register has a corresponding CLR
(clear), SET (set) and INV (invert) register designed to
provide fast atomic bit manipulations. As the name of
the register implies, a value written to a SET, CLR or
INV register effectively performs the implied operation,
but only on the corresponding base register and only
bits specified as ‘ 1 ’ are modified. Bits specified as ‘ 0 ’
are not modified.
Reading SET, CLR and INV registers returns undefined
values. To see the affects of a write operation to a SET,
CLR or INV register, the base register must be read.
12.1.2
Pins are configured as digital inputs by setting the
corresponding TRIS register bits = 1 . When configured
as inputs, they are either TTL buffers or Schmitt
Triggers. Several digital pins share functionality with
analog inputs and default to the analog inputs at POR.
Setting the corresponding bit in the AD1PCFG register
= 1 enables the pin as a digital pin.
DS61156F-page 130
Note:
Parallel I/O (PIO) Ports
reads
CLR, SET AND INV REGISTERS
Using a PORTxINV register to toggle a bit
is recommended because the operation is
performed in hardware atomically, using
fewer instructions, as compared to the
traditional
shown below:
DIGITAL INPUTS
PORTC ^= 0x0001 ;
the
last
read-modify-write
value
written
method
to
the
The maximum input voltage allowed on the input pins
is the same as the maximum V
Section 31.0 “Electrical Characteristics”
specification details.
12.1.3
Certain pins can be configured as analog inputs used
by the ADC and comparator modules. Setting the
corresponding bits in the AD1PCFG register = 0
enables the pin as an analog input pin and must have
the corresponding TRIS bit set = 1 (input). If the TRIS
bit is cleared = 0 (output), the digital output level (V
or V
configured as analog, its digital input is disabled and
the corresponding PORTx register bit will read ‘ 0 ’. The
AD1PCFG register has a default value of 0x0000 ;
therefore, all pins that share ANx functions are analog
(not digital) by default.
12.1.4
Pins are configured as digital outputs by setting the
corresponding TRIS register bits = 0 . When configured
as digital outputs, these pins are CMOS drivers or can
be configured as open-drain outputs by setting the
corresponding
Configuration register.
The open-drain feature allows generation of outputs
higher than V
pins by using external pull-up resistors. The maximum
open-drain voltage allowed is the same as the
maximum V
See the
and their functionality.
12.1.5
Certain pins can be configured as analog outputs, such
as the CV
module. Configuring the comparator reference module
to provide this output will present the analog output
voltage on the pin, independent of the TRIS register
setting for the corresponding pin.
12.1.6
The input change notification function of the I/O ports
(CNx) allows devices to generate interrupt requests in
response to change of state on selected pin.
Each CNx pin also has a weak pull-up, which acts as a
current source connected to the pin. The pull-ups are
enabled by setting corresponding bit in CNPUE
register.
Note:
OL
) will be converted. Any time a port I/O pin is
“Pin
REF
Analog levels on any pin that is defined as
a digital input (including the ANx pins)
may cause the input buffer to consume
current
specifications.
ANALOG INPUTS
DIGITAL OUTPUTS
ANALOG OUTPUTS
INPUT CHANGE NOTIFICATION
IH
DD
Diagrams” section for the available pins
specification.
output voltage used by the comparator
bits
(e.g., 5V) on any desired 5V tolerant
that
in
© 2010 Microchip Technology Inc.
the
exceeds
IH
specification. Refer to
ODCx
the
Open-Drain
for V
device
OH
IH