PIC32MX664F064HT-I/PT Microchip Technology, PIC32MX664F064HT-I/PT Datasheet - Page 48

• Manufacturer Part Number: PIC32MX664F064HT-I/PT
• Description: 64 PINS, 64KB Flash, 32KB RAM, 80 MHz, USB, Ethernet, 4 DMA 64 TQFP 10x10x1mm T/
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX664F064HT-I/PT

• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: Ethernet, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Processor Series: PIC32MX5x
• Core: MIPS32
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC32MX5XX/6XX/7XX
TABLE 3-2:
DS61156F-page 48
Note 1:
Register
Number
17-22
25-29
0-6
10
11
12
12
12
12
13
14
15
15
16
16
16
16
23
24
30
31
7
8
9
2:
Registers used in exception processing.
Registers used during debug.
Reserved
HWREna
BadVAddr
Count
Reserved
Compare
Status
IntCtl
SRSCtl
SRSMap
Cause
EPC
PRId
EBASE
Config
Config1
Config2
Config3
Reserved
Debug
DEPC
Reserved
ErrorEPC
DESAVE
(1)
(1)
Register
(1)
COPROCESSOR 0 REGISTERS
(1)
(2)
(1)
(2)
Name
(1)
(1)
(2)
(1)
(1)
(1)
Reserved in the PIC32MX5XX/6XX/7XX family core.
Enables access via the RDHWR instruction to selected hardware registers.
Reports the address for the most recent address-related exception.
Processor cycle count.
Reserved in the PIC32MX5XX/6XX/7XX family core.
Timer interrupt control.
Processor status and control.
Interrupt system status and control.
Shadow register set status and control.
Provides mapping from vectored interrupt to a shadow set.
Cause of last general exception.
Program counter at last exception.
Processor identification and revision.
Exception vector base register.
Configuration register.
Configuration Register 1.
Configuration Register 2.
Configuration Register 3.
Reserved in the PIC32MX5XX/6XX/7XX family core.
Debug control and exception status.
Program counter at last debug exception.
Reserved in the PIC32MX5XX/6XX/7XX family core.
Program counter at last error.
Debug handler scratchpad register.
Function
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