PIC32MX664F064HT-I/PT Microchip Technology, PIC32MX664F064HT-I/PT Datasheet - Page 45

• Manufacturer Part Number: PIC32MX664F064HT-I/PT
• Description: 64 PINS, 64KB Flash, 32KB RAM, 80 MHz, USB, Ethernet, 4 DMA 64 TQFP 10x10x1mm T/
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX664F064HT-I/PT

• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: Ethernet, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Processor Series: PIC32MX5x
• Core: MIPS32
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.0
The
PIC32MX5XX/6XX/7XX family processor. The MCU
fetches instructions, decodes each instruction, fetches
source operands, executes each instruction and writes
the results of instruction execution to the proper
destinations.
3.1
• 5-stage pipeline
• 32-bit address and data paths
• MIPS32 Enhanced Architecture (Release 2)
FIGURE 3-1:
© 2010 Microchip Technology Inc.
- Multiply-accumulate and multiply-subtract
- Targeted multiply instruction
- Zero/One detect instructions
- WAIT instruction
- Conditional move instructions (MOVN, MOVZ)
- Vectored interrupts
- Programmable exception vector base
Note 1: This data sheet summarizes the features
instructions
MCU
2: Some registers and associated bits
PIC32 MCU
Features
MCU
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 2. “MCU”
(DS61113)
Reference Manual”, which is available
from the Microchip web site
chip.com/PIC32). Resources for the
MIPS32
available at http://www.mips.com.
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
module
®
MCU BLOCK DIAGRAM
M4K
(RF/ALU/Shift)
Coprocessor
in
is
Execution
®
System
Core
MDU
the
the
Processor Core are
“PIC32
heart
(www.micro-
of
Family
FMT
the
in
• MIPS16e
• Simple Fixed Mapping Translation (FMT)
• Simple dual bus interface
• Autonomous multiply/divide unit
• Power control
• EJTAG debug and instruction trace
Bus Interface
Management
PIC32MX5XX/6XX/7XX
- Atomic interrupt enable/disable
- GPR shadow registers to minimize latency
- Bit field manipulation instructions
- 16-bit encoding of 32-bit instructions to
- Special PC-relative instructions for efficient
- SAVE and RESTORE macro instructions for
- Improved support for handling 8 and 16-bit
mechanism
- Independent 32-bit address and data busses
- Transactions can be aborted to improve
- Maximum issue rate of one 32x16 multiply
- Maximum issue rate of one 32x32 multiply
- Early-in iterative divide. Minimum 11 and
- Minimum frequency: 0 MHz
- Low-Power mode (triggered by WAIT
- Extensive use of local gated clocks
- Support for single stepping
- Virtual instruction and data address/value
- Breakpoints
- PC tracing with trace compression
for interrupt handlers
improve code density
loading of addresses and constants
setting up and tearing down stack frames
within subroutines
data types
interrupt latency
per clock
every other clock
maximum 33 clock latency (dividend (rs) sign
extension-dependent)
instruction)
Power
EJTAG
Trace
TAP
®
code compression
Dual Bus I/F
Debug I/F
Off-Chip
Trace I/F
DS61156F-page 45