S29PL064J70BFI120 Spansion Inc., S29PL064J70BFI120 Datasheet - Page 59

• Manufacturer Part Number: S29PL064J70BFI120
• Description: Flash Memory
• Manufacturer: Spansion Inc.

15.5
December 18, 2009 S29PL-J_00_A12
15.5.1
Word Program Command Sequence
Unlock Bypass Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two
unlock write cycles, followed by the program set-up command. The program address and data are written
next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further
controls or timings. The device automatically provides internally generated program pulses and verifies the
programmed cell margin.
command sequence. Note that the Secured Silicon Sector, autoselect, and CFI functions are unavailable
when a [program/erase] operation is in progress.
When the Embedded Program algorithm is complete, that bank then returns to the read mode and addresses
are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or
RY/BY#. Refer to
Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program operation. The program command sequence should be
reinitiated once that bank has returned to the read mode, to ensure data integrity. Note that the Secured
Silicon Sector, autoselect and CFI functions are unavailable when the Secured Silicon Sector is enabled.
Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from
“0” back to a “1.” Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6
status bits to indicate the operation was successful. However, a succeeding read will show that the data is still
“0.” Only erase operations can convert a “0” to a “1.”
The unlock bypass feature allows the system to program data to a bank faster than using the standard
program command sequence. The unlock bypass command sequence is initiated by first writing two unlock
cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank then
enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is
required to program in this mode. The first cycle in this sequence contains the unlock bypass program
command, A0h; the second cycle contains the program address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial two unlock cycles required in the standard program
command sequence, resulting in faster total programming time.
requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are
valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command
sequence. (See
The device offers accelerated program operations through the WP#/ACC pin. When the system asserts V
on the WP#/ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write
the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/
ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at V
accelerated programming, or device damage may result. In addition, the WP#/ACC pin must not be left
floating or unconnected; inconsistent behavior of the device may result.
Figure 15.1 on page 60
Operations on page 78
Table 15.2 on page
Write Operation Status on page 66
for parameters, and
illustrates the algorithm for the program operation. Refer to the table
D a t a
Table 15.1 on page 64
S h e e t
65)
S29PL-J
Figure 20.6 on page 79
shows the address and data requirements for the program
for information on these status bits.
Table 15.1 on page 64
for timing diagrams.
HH
any operation other than
shows the
Erase/Program
HH
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