SP706SCN-L Exar Corporation, SP706SCN-L Datasheet - Page 12

Low Power Microprocessor Supervisory Circuits

SP706SCN-L

Manufacturer Part Number
SP706SCN-L
Description
Low Power Microprocessor Supervisory Circuits
Manufacturer
Exar Corporation
Type
Simple Reset/Power-On Resetr
Datasheet

Specifications of SP706SCN-L

Number Of Voltages Monitored
1
Reset
Active Low
Reset Timeout
140 ms Minimum
Voltage - Threshold
2.93V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (0.154", 3.90mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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resistors and transistor as shown, a HIGH PFO
triggers RESET. As long as PFO remains HIGH,
the SP706R/S/T-SP708R/S/T series will keep
RESET asserted (where RESET = LOW and
RESET = HIGH). Note that this circuit's
accuracy
tolerance, the V
© 2010 Exar Corporation
Fig. 21: Monitoring +3.3V/+3.0V and +12V Power
Fig. 22: Monitoring a Negative Voltage Supply
depends
CC
line, and the resistors.
Supplies
on
the
PFI
3
3
.
.
0
0
V
V
threshold
/
/
3
3
.
.
3
3
V
V
L
L
12/16
o
o
w
w
I
RESET P
µPs with bidirectional RESET pins, such as the
Motorola 68HC11 series, can contend with the
SP705/706/707/708 RESET output. If, for
example, the RESET output is driven HIGH and
the µP wants to pull it LOW, indeterminate
logic
connect a 4.7KΩ resistor between the RESET
output and the µP reset I/O, as shown if
Figure 23. Buffer the RESET output to other
system components.
N
While issuing resets to the μP during power-
up, power-down, and brownout conditions,
these supervisors are relatively immune to
short duration negative-going VCC transients
(glitches). It is usually undesirable to reset the
μP when V
Figure 24 shows maximum transient duration
vs. reset-comparator overdrive, for which
reset pulses are not generated. The data was
generated using negative-going V
starting at 3.3V and ending below the reset
threshold by the magnitude indicated (reset
comparator overdrive). The graph shows the
maximum pulse width a negative-going V
transient may typically have without causing a
reset pulse to be issued. As the amplitude of
the transient increases (i.e. goes farther below
P
P
NTERFACING TO µ
EGATIVE
o
o
w
w
S
S
P
P
e
e
levels
r
r
Fig. 23: Interfacing to Microprocessors
7
7
with Bidirectional RESET I/O (SP706)
INS
M
M
0
0
CC
-G
i
6
i
6
experiences only small glitches.
c
c
OING
R
R
may
r
r
o
o
/
/
p
p
S
S
r
r
P
V
o
o
/
/
result.
S WITH
CC
c
c
T
T
e
e
T
s
s
-
-
RANSIENT
s
s
S
S
o
o
r
P
r
B
To
P
IDIRECTIONAL
S
S
7
7
u
u
0
0
correct
p
p
8
8
e
e
CC
C
C
R
R
r
Rev. 2.0.0
r
i
i
v
v
/
/
r
r
pulses,
i
i
c
c
S
s
s
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u
u
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this,
o
/
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i
r
r
t
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s
s

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