ISP1504CBSTM STEricsson, ISP1504CBSTM Datasheet - Page 24

• Manufacturer Part Number: ISP1504CBSTM
• Manufacturer: STEricsson

Specifications of ISP1504CBSTM

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Operating Supply Voltage (typ): Not RequiredV
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): Not RequiredV
• Operating Supply Voltage (min): Not RequiredV
• Pin Count: 32
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
ISP1504A_ISP1504C_3
Product data sheet
Fig 7.
DATA[7:0]
RESET_N
CLOCK
NXT
STP
DIR
Interface behavior with respect to RESET_N
9.3.2 Interface behavior with respect to RESET_N
9.3.3 Interface behavior with respect to CHIP_SELECT_N
Hi-Z (input)
Hi-Z (input)
The interface protect feature can be disabled by setting the INTF_PROT_DIS bit to logic 1.
The use of the RESET_N pin is optional. When RESET_N is asserted (LOW), the
ISP1504 will assert DIR. All logic in the ISP1504 will be reset, including the analog
circuitry and ULPI registers. During reset, the link must drive DATA[7:0] and STP to LOW;
otherwise undefined behavior may result. When RESET_N is deasserted (HIGH), the DIR
output will deassert (LOW) four or five clock cycles later.
interface behavior when RESET_N is asserted (LOW), and subsequently deasserted
(HIGH). The behavior of
(LOW). If RESET_N is not used, it must be connected to V
At any time that CHIP_SELECT_N is HIGH, the ISP1504 will 3-state DATA[7:0], NXT and
DIR. In addition, the STP input will be ignored. The link can reuse these pins for other
purposes.
When CHIP_SELECT_N is LOW, ULPI output pins operate normally. During normal
operation, the PLL is always powered, regardless of the level of CHIP_SELECT_N.
During power-up, if CHIP_SELECT_N is HIGH, the PLL is not powered up to reduce
power consumption. During power-up, if CHIP_SELECT_N is LOW, the PLL is powered
and the ISP1504 operates normally.
If CHIP_SELECT_N is HIGH:
•
•
•
•
The DATA[7:0], NXT and DIR pins are 3-stated and ignored.
If the ISP1504 was previously in synchronous mode, the STP pin is ignored. If the
ISP1504 was previously in serial or suspend mode, STP is used to exit.
The pull-down resistors on DATA[7:0] are disabled.
The ULPI controller is forced into an idle state and any ULPI command is ignored.
Hi-Z (link must drive)
Hi-Z (link must drive)
Rev. 03 — 7 April 2008
Figure 7
applies only when CHIP_SELECT_N is asserted
Hi-Z (input)
Hi-Z (input)
ISP1504A; ISP1504C
Figure 7
ULPI HS USB OTG transceiver
CC(I/O)
.
shows the ULPI
© NXP B.V. 2008. All rights reserved.
004aaa720
23 of 82