ISP1705AETTM

Manufacturer Part NumberISP1705AETTM
ManufacturerSTEricsson
ISP1705AETTM datasheet
 


Specifications of ISP1705AETTM

Lead Free Status / RoHS StatusCompliant  
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IMPORTANT NOTICE 

ISP1705AETTM Summary of contents

  • Page 1

    ... If you have any questions related to the document, please contact our  nearest sales office or wired.support@stericsson.com.  Thank you for your cooperation and understanding.      ...

  • Page 2

    ISP1705 ULPI Hi-Speed USB transceiver Rev. 02 — 21 January 2009 1. General description The ISP1705 is a UTMI+ Low Pin Interface (ULPI) Hi-Speed Universal Serial Bus (USB) transceiver that is fully compliant with Universal Serial Bus Specification Rev. 2.0, ...

  • Page 3

    Complete USB OTG physical front-end that supports Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) Supports external charge pump or external V Complete control over USB termination resistors Data line and V Integrated V Integrated cable (ID) detector Flexible ...

  • Page 4

    Available in small HVQFN36 and TFBGA36 Restriction of Hazardous Substances (RoHS) compliant, halogen-free and lead-free packages 3. Applications Digital still camera Digital TV Digital Video Disc (DVD) recorder External storage device, for example: Magneto-Optical (MO) drive Optical drive (CD-ROM, CD-RW, ...

  • Page 5

    Block diagram 29 CLOCK 1, 2, 24, 25, 27, 28, 8 30, 36 DATA ULPI [7:0] INTERFACE 19 DIR 22 STP 23 NXT 7 CFG0 34 CHIP_SEL_N CHIP_SEL 35 31 CFG1 32 CFG2 GLOBAL CLOCKS 16 XTAL1 17 XTAL2 ...

  • Page 6

    Pinning information 7.1 Pinning Fig 2. Pin configuration HVQFN36 Fig 3. Pin configuration TFBGA36 ISP1705_2 Product data sheet terminal 1 index area DATA1 1 DATA0 CC(I/O) RREF 4 ISP1705HN CFG0 7 V ...

  • Page 7

    Pin description Table 3. Pin description [1] Symbol Pin HVQFN36 TFBGA36 (ISP1705HN) (ISP1705AET) DATA1 1 A1 DATA0 CC(I/O) RREF CFG0 ...

  • Page 8

    Table 3. Pin description …continued [1] Symbol Pin HVQFN36 TFBGA36 (ISP1705HN) (ISP1705AET) XTAL1 16 F5 XTAL2 17 F6 REG1V8 18 E6 DIR 19 E5 RESET_N CC(I/O) STP 22 D6 NXT 23 D5 DATA7 24 C6 ...

  • Page 9

    Table 3. Pin description …continued [1] Symbol Pin HVQFN36 TFBGA36 (ISP1705HN) (ISP1705AET) CHIP_SEL 35 - DATA2 36 A2 GND exposed die - pad [1] Symbol names ending with underscore N (for example, NAME_N) indicate active-LOW signals. [ input; ...

  • Page 10

    Functional description 8.1 ULPI interface controller The ISP1705 provides a 12-pin interface that is compliant with UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1. This interface must be connected to a USB link. The ULPI interface controller provides the ...

  • Page 11

    High-speed disconnect detector • 45 high-speed bus terminations on pins DP and DM • 1.5 k • bus terminations on pins DP and DM For details on controlling resistor settings, see 8.4 Voltage regulator The ISP1705 contains ...

  • Page 12

    OTG module This module contains several sub-blocks that provide all the functionality required by the USB OTG specification. Specifically, it provides the following circuits: • The ID detector to sense the ID pin of the micro-USB cable. The ID ...

  • Page 13

    SRP charge and discharge resistors The ISP1705 provides on-chip resistors for short-term charging and discharging of V These are used by the B-device to request a session, prompting the A-device to restore the V voltage. First, the B-device makes ...

  • Page 14

    Fig 5. Internal power-on reset timing 8.11 Power-up, reset and bus idle sequence Figure 6 shows a typical start-up sequence. On power-up, the ISP1705 performs an internal power-on reset and asserts DIR to indicate to the link that the ULPI ...

  • Page 15

    CC(I/O) CHIP_SEL_N REG1V8 t PWRUP Internal POR XTAL1 CLOCK (output) DATA[7:0] DIR STP NXT applied to the ISP1705 turned on. ULPI interface pins CLOCK, DATA[7:0], ...

  • Page 16

    Interface protection By default, the ISP1705 enables a weak pull-up resistor on STP. If the STP pin is unexpectedly HIGH at any time, the ISP1705 will protect the ULPI interface by enabling weak pull-down resistors on DATA[7:0]. The interface ...

  • Page 17

    Interface behavior with respect to chip select The use of chip select as a power-down control signal is optional. When chip select is deasserted, the ISP1705 will 3-state ULPI pins and power-down the internal circuitry. If chip select is ...

  • Page 18

    DATA[7:0] • DIR • NXT • STP • RESET_N 8.12.3 RREF Resistor reference analog I/O pin RREF pin and GND. This provides an accurate voltage reference that biases internal analog circuitry. Less accurate resistors cannot be ...

  • Page 19

    If an external V of that circuit can be connected to the FAULT input pin. The USE_EXT_VBUS_IND bit in the OTG_CTRL register (see INTF_CTRL register (see link of V BUS The FAULT input pin is mapped to the A_VBUS_VLD bit ...

  • Page 20

    Fig 9. V 8.12.11 PSW_N The PSW_N pin is an active-LOW open-drain output pin used to control external charge pumps or V resistor is required. This allows for per-port or ganged power control. To enable the external power ...

  • Page 21

    If a crystal is attached, it requires a capacitor on each terminal of the crystal to GND. The recommended crystal specification and required external capacitors are given in and Table Table 7. Load capacitance C [1] crystal ...

  • Page 22

    ISP1705 is sending data to the link, NXT will be asserted to notify the link that another valid byte is on the bus. NXT is not used for register read data or the RXCMD status update. This pin ...

  • Page 23

    Modes of operation 9.1 Power modes When both V to all the remaining pins, including V range will not damage the ISP1705 chip. When both V ISP1705 will be fully functional as in normal mode. When V CC(I/O) ISP1705, ...

  • Page 24

    When the ISP1705 is put into Power-down mode by disabling chip select, all the digital pins (see Section inputs. These pins must be driven to defined states or terminated by using pull-up or pull-down resistors to avoid a floating input ...

  • Page 25

    Table 10. ULPI signal description Signal name Direction on Signal description [1] the ISP1705 DIR O Direction: Controls the direction of data bus DATA[7:0]. In synchronous mode, the ISP1705 drives DIR to LOW by default, making the data bus an ...

  • Page 26

    Table 11. Signal Reserved INT Reserved [ input output. 9.2.3 6-pin full-speed or low-speed serial mode If the link requires a 6-pin serial interface to transmit and receive full-speed or low-speed USB data, it can set ...

  • Page 27

    For more information on 3-pin serial mode enter and exit protocols, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1. Table 13. Signal TX_ENABLE DAT SE0 INT Reserved [ input output. 9.2.5 Transparent UART mode ...

  • Page 28

    Set the XCVRSELECT[1:0] bits in the FUNC_CTRL register (see (low speed) or 01b (full speed). This setting affects the rise time and the fall time of the UART transmitting signal on the DM line. 2. Set the DP_PULLDOWN and ...

  • Page 29

    CLOCK (2) CLOCK DATA[7:0] DIR STP NXT UART mode (1) Clock remains powered when the CLOCK_SUSPENDM register bit is set to logic 1. (2) Clock is powered down when the CLOCK_SUSPENDM register bit is logic 0 (default). Fig 10. ...

  • Page 30

    USB state transitions A Hi-Speed USB peripheral, host or OTG device handles more than one electrical state as defined in Universal Serial Bus Specification Rev. 2.0 and On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3. The ISP1705 accommodates ...

  • Page 31

    Table 15. Operating states and their corresponding resistor settings Signaling mode Register settings XCVR TERM SELECT SELECT [1:0] Peripheral high 01b 1b speed or full speed suspend Peripheral high 01b 1b speed or full speed resume Peripheral Test J or ...

  • Page 32

    Protocol description 10.1 ULPI references The ISP1705 provides a 12-pin ULPI interface to communicate with the link highly recommended that users of the ISP1705 read UTMI+ Specification Rev. 1.0 and UTMI+ Low Pin Interface (ULPI) Specification Rev. ...

  • Page 33

    The ISP1705 will automatically send an RXCMD whenever there is a change in any of the RXCMD data fields. The link must be able to accept an RXCMD at any time; including single RXCMDs, back-to-back RXCMDs, and RXCMDs at any ...

  • Page 34

    Table 18. DP_PULLDOWN = 0. Mode XCVRSELECT[1:0] TERMSELECT LINESTATE[1:0] [1] !squelch indicates inactive squelch. !HS_Differential_Receiver_Output indicates inactive HS_Differential_Receiver_Output. Table 19. DP_PULLDOWN and DM_PULLDOWN = 1. Mode XCVRSELECT[1:0] TERMSELECT OPMODE[1:0] LINESTATE[1:0] [1] !squelch indicates inactive squelch. !HS_Differential_Receiver_Output indicates inactive HS_Differential_Receiver_Output. 10.3.2 ...

  • Page 35

    The A_VBUS_VLD indicator in the V configured based on current draw requirements. A_VBUS_VLD can input from one or more V BUS A description on how to use and select the V USE_EXT_VBUS_IND, IND_PASSTHRU Fig 13. RXCMD A_VBUS_VLD indicator source 10.3.3 ...

  • Page 36

    not necessary to qualify the fault indicator with the internal A_VBUS_VLD comparator, set the IND_PASSTHRU bit in the INTF_CTRL register (see Section 10.3.3.2 Standard USB peripheral controllers Standard peripherals must be able to detect when V ...

  • Page 37

    RxError When the ISP1705 has detected an error while receiving a USB packet, it deasserts NXT and sends an RXCMD with the RxError field set to logic 1. The received packet is no longer valid and must be dropped ...

  • Page 38

    USB reset: The host detects a peripheral attachment as low-speed HIGH and as full-speed HIGH host detects a low-speed peripheral, it does not follow the remainder of this protocol ...

  • Page 39

    USB reset t0 TXCMD (REGW) SE0 DATA [7:0] DIR STP NXT 01 (FS) XCVR SELECT TERM SELECT 00 (normal) OP MODE J (01b) SE0 (00b) LINE STATE TXCMD SE0 (REGW) DATA [7:0] DIR STP NXT 01 (FS) XCVR SELECT TERM ...

  • Page 40

    USB packet transmit and receive An example of a packet transmit and receive is shown in packets, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1. link sends TXCMD CLOCK DATA [ 7:0 ] TXCMD DIR STP NXT ...

  • Page 41

    Table 24. Link decision times Packet sequence High-speed Full-speed link delay link delay Transmit-Transmit (host only) Receive-Transmit (host or peripheral) Receive-Receive 1 1 (peripheral only) Transmit-Receive 92 80 ...

  • Page 42

    DP or DATA EOP DM CLOCK DATA [7: DIR STP NXT RX end delay (three to eight clocks) Fig 18. High-speed receive-to-transmit packet timing 10.7 Preamble ...

  • Page 43

    CLOCK DATA[7:0] DIR STP NXT and DM timing is not to scale. Fig 19. Preamble sequence 10.8 USB suspend and resume 10.8.1 Full-speed or low-speed host-initiated suspend and resume Figure 20 suspend and sometime later initiates ...

  • Page 44

    DATA [ 7:0 ] DIR STP NXT OPMODE 00b LINE J STATE CLOCK TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT OPMODE SUSPENDM LINE STATE DP DM Timing is not to scale. Fig 20. Full speed suspend and ...

  • Page 45

    The sequence of events related to a host and a peripheral, both with ISP1705 follows: 1. High speed idle: Initially, the host and the peripheral are idle. The host has its 15 k pull-down resistors enabled (DP_PULLDOWN and ...

  • Page 46

    HS idle TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT XCVR 00b SELECT TERM SELECT OP MODE !SQUELCH SQUELCH (01b) (00b) LINE STATE CLOCK TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT XCVR 00b SELECT TERM SELECT OP ...

  • Page 47

    Remote wake-up The ISP1705 supports peripherals that initiate remote wake-up resume. When placed into USB suspend, the peripheral link remembers at what speed it was originally operating. Depending on the original speed, the link follows one of the protocols ...

  • Page 48

    LINESTATE DATA [ 7:0 ] DIR STP NXT XCVR SELECT TERM SELECT OP MODE TXCMD LINESTATE REGW DATA [ 7:0 ] DIR STP NXT XCVR SELECT TERM SELECT OP MODE Timing is not to scale. Fig 22. Remote wake-up from ...

  • Page 49

    PHY will not transmit any EOP. The ISP1705 will also detect if the PID byte is A5h, indicating an SOF packet, and automatically send a long EOP when STP is asserted. To transmit chirp and resume signaling, the link must ...

  • Page 50

    OTG comparators The ISP1705 provides comparators that conform to On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3 requirements of V and V B_SESS_END V A_SESS_VLD are communicated to the link by RXCMDs as described in comparators is described ...

  • Page 51

    SYNC DATA0 (TX_ENABLE) DATA1 (TX_DAT) DATA2 (TX_SE0) DATA4 (RX_DP) DATA5 (RX_DM) DATA6 (RX_RCV Fig 24. Example of transmit followed by receive in 6-pin serial mode SYNC DATA0 (TX_ENABLE) DATA1 (TX_DAT/ RX_RCV) DATA2 (TX_SE0/ RX_SE0 Fig 25. ...

  • Page 52

    Aborting transfers The ISP1705 supports aborting transfers on the ULPI bus. For details, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1, Section 3.8.4. 10.13 Avoiding contention on the ULPI data bus Because the ULPI data bus is ...

  • Page 53

    Register map Table 25. Register map Field name Size (bit) VENDOR_ID_LOW 8 VENDOR_ID_HIGH 8 PRODUCT_ID_LOW 8 PRODUCT_ID_HIGH 8 FUNC_CTRL 8 INTF_CTRL 8 OTG_CTRL 8 USB_INTR_EN_R 8 USB_INTR_EN_F 8 USB_INTR_STAT 8 USB_INTR_L 8 DEBUG 8 SCRATCH 8 CARKIT_CTRL 8 Reserved ...

  • Page 54

    PRODUCT_ID_LOW register The bit description of the register is given in Table 28. Legend: * reset value Bit Symbol PRODUCT_ID_ LOW[7:0] 11.4 PRODUCT_ID_HIGH register The bit description of the register is given in Table 29. Legend: ...

  • Page 55

    Table 31. FUNC_CTRL - Function control register (address R = 04h to 06h 04h 05h 06h) bit description …continued Bit Symbol Description OPMODE[1:0] Operation mode: Selects the required bit-encoding style during ...

  • Page 56

    INTF_CTRL register The INTF_CTRL register enables alternative interfaces. All of these modes are optional features provided for legacy link cores. Setting more than one of these fields results in undefined behavior. Table 32. INTF_CTRL - Interface control register (address ...

  • Page 57

    Table 33. Bit Symbol 2 CARKIT_MODE 1 3PIN_FSLS_SERIAL 0 6PIN_FSLS_SERIAL 11.7 OTG_CTRL register This register controls various OTG functions of the ISP1705. The bit allocation of the OTG_CTRL register is given in Table 34. OTG_CTRL - OTG control register (address ...

  • Page 58

    Table 35. Bit Symbol 7 USE_EXT_ VBUS_IND 6 DRV_VBUS_EXT 5 reserved 4 CHRG_VBUS 3 DISCHRG_VBUS 2 DM_PULLDOWN 1 DP_PULLDOWN 0 ID_PULLUP ISP1705_2 Product data sheet OTG_CTRL - OTG control register (address R = 0Ah to 0Ch 0Ah, S ...

  • Page 59

    USB_INTR_EN_R register The bits in this register enable interrupts and RXCMDs to be sent when the corresponding bits in the USB_INTR_STAT register change from logic 0 to logic 1. By default, all transitions are enabled. Table 36. USB_INTR_EN_R - ...

  • Page 60

    Table 39. Bit Symbol ID_GND_F 3 SESS_END_F 2 SESS_VALID_F 1 VBUS_VALID_F 0 HOST_DISCON_F 11.10 USB_INTR_STAT register This register (see Table 40. USB_INTR_STAT - USB interrupt status register (address R = 13h) bit allocation Bit 7 ...

  • Page 61

    Table 42. USB_INTR_L - USB interrupt latch register (address R = 14h) bit allocation Bit 7 6 Symbol reserved Reset 0 0 Access R R Table 43. Bit Symbol reserved 4 ID_GND_L 3 SESS_END_L 2 SESS_VALID_L 1 ...

  • Page 62

    SCRATCH register This is a 1-byte empty register for testing purposes, see Table 46. Bit Symbol SCRATCH[7:0] 11.14 CARKIT_CTRL register This register controls transparent UART mode. This register is only valid when the CARKIT_MODE bit in ...

  • Page 63

    PWR_CTRL register This vendor-specific register controls the power feature of the ISP1705. The bit allocation of the register is given in Table 49. PWR_CTRL - Power control register (address R = 3Dh to 3Fh 3Dh ...

  • Page 64

    Limiting values Table 51. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC V input/output supply voltage CC(I/O) V input voltage I V electrostatic discharge ESD voltage I latch-up current ...

  • Page 65

    Static characteristics Table 53. Static characteristics: supply pins CC(I/O) Typical values refer 3 Symbol Parameter V power-on ...

  • Page 66

    Table 55. Static characteristics: digital pins Digital pins: CLOCK, DIR, STP, NXT, DATA[7:0], CHIP_SEL_N, CHIP_SEL, CFG1, CFG2 and RESET_N; unless otherwise specified CC(I/O) Typical ...

  • Page 67

    Table 58. Static characteristics: analog pins (DP CC(I/O) Typical values refer 3 Symbol Parameter Original USB transceiver ...

  • Page 68

    Table 58. Static characteristics: analog pins (DP CC(I/O) Typical values refer 3 Symbol Parameter Leakage current I ...

  • Page 69

    Table 60. Static characteristics: analog pin CFG0 CC(I/O) Symbol Parameter Input levels V LOW-level input voltage IL V HIGH-level input voltage IH I input ...

  • Page 70

    Dynamic characteristics Table 65. Dynamic characteristics: reset and power CC(I/O) Symbol Parameter t internal power-on reset W(POR) pulse width t REG1V8 HIGH pulse ...

  • Page 71

    Table 68. Dynamic characteristics: digital I/O pins (SDR CC(I/O) Symbol Parameter t STP set-up time with respect to su(STP) the rising edge of pin ...

  • Page 72

    Table 70. Dynamic characteristics: analog I/O pins (DP, DM) in USB mode CC(I/O) Symbol Parameter High-speed driver characteristics; see t rise time (10 % ...

  • Page 73

    Table 72. Dynamic characteristics: analog I/O pins (DP, DM) in serial mode CC(I/O) Symbol Parameter Driver timing (valid only for serial mode) t driver ...

  • Page 74

    CLOCK CONTROL IN (STP) DATA IN (8-BIT) CONTROL OUT (DIR, NXT) DATA OUT (8-BIT) Fig 30. ULPI timing interface 16. Application information Table 73. Recommended bill of materials Designator Application C highly recommended for all bypass applications C highly recommended ...

  • Page 75

    C bypass C bypass R S(VBUS) V BUS USB STANDARD-B GND RECEPTACLE 4 C VBUS SHIELD 5 SHIELD 6 This figure shows the HVQFN pinout. For the ...

  • Page 76

    V IN FAULT V BUS R pullup SWITCH C bypass ON OUT C bypass V BUS USB GND 5 MICRO-AB RECEPTACLE C VBUS A1 ...

  • Page 77

    V IN FAULT V BUS R pullup SWITCH C bypass ON OUT V BUS USB 3 STANDARD-A RECEPTACLE GND C VBUS 4 SHIELD 5 SHIELD 6 C ...

  • Page 78

    Package outline HVQFN36: plastic thermal enhanced very thin quad flat package; no leads; 36 terminals; body 0.85 mm terminal 1 index area terminal 1 36 index area DIMENSIONS ...

  • Page 79

    TFBGA36: plastic thin fine-pitch ball grid array package; 36 balls; body 3.5 x 3.5 x 0.8 mm ball A1 index area 1 ball index area DIMENSIONS (mm are the ...

  • Page 80

    Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 18.1 Introduction to soldering Soldering ...

  • Page 81

    Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, ...

  • Page 82

    MSL: Moisture Sensitivity Level Fig 36. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 19. Abbreviations Table 76. Acronym ASIC ATX CD-DVD CDM CD-ROM ...

  • Page 83

    Table 76. Acronym MM NRZI OTG PDA PHY PID PLL POR RoHS RXCMD RXD SDR SE0 SOC SOF SRP SYNC TTL TXCMD TXD UART ULPI USB USB-IF UTMI UTMI+ WLCSP 20. Glossary A-device — An OTG device with an attached ...

  • Page 84

    UTMI+ Specification Rev. 1.0 [5] USB 2.0 Transceiver Macrocell Interface (UTMI) Specification Ver. 1.05 [6] Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) (JESD22-A114D) [7] Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM) (JESD22-A115-A) [8] Field-Induced Charged-Device Model ...

  • Page 85

    Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 2. Marking codes . . . . . . . . . ...

  • Page 86

    Table 51. Limiting values . . . . . . . ...

  • Page 87

    Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Fig 2. Pin configuration HVQFN36 . ...

  • Page 88

    Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . ...

  • Page 89

    Pull-up and pull-down resistors 10.10.3 ID detection . . . . . . . . . . . . . . . . . . . . ...

  • Page 90

    Information in this document is provided solely in connection with ST-NXP products. ST-NXP Wireless NV and its subsidiaries (“ST-NXP”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at ...