ISP1705AETTM STEricsson, ISP1705AETTM Datasheet - Page 42

• Manufacturer Part Number: ISP1705AETTM
• Manufacturer: STEricsson

Specifications of ISP1705AETTM

• Lead Free Status / RoHS Status: Compliant

ISP1705_2
Product data sheet
Fig 18. High-speed receive-to-transmit packet timing
CLOCK
DP or
DATA
[7:0]
STP
NXT
DIR
DM
D
N 4
DATA
D
10.7 Preamble
N 3
D
EOP
N 2
Preamble packets are headers to low-speed packets that must travel over a full-speed
bus, between a host and a hub. To enter preamble mode, the link sets
XCVRSELECT[1:0] = 11b in the FUNC_CTRL register (see
preamble mode, the ISP1705 operates just as in full-speed mode, and sends all data with
the full-speed rise time and fall time. Whenever the link transmits a USB packet in
preamble mode, the ISP1705 will automatically send a preamble header at full-speed bit
rate before sending the link packet at low-speed bit rate. The ISP1705 will ensure a
minimum gap of four full-speed bit times between the last bit of the full-speed PRE PID
and the first bit of the low-speed packet SYNC. The ISP1705 will drive a J for at least one
full-speed bit time after sending the PRE PID, after which the pull-up resistor can hold the
J state on the bus. An example transmit packet is shown in
In preamble mode, the ISP1705 can also receive low-speed packets from the full-speed
bus.
(three to eight clocks)
D
RX end delay
N 1
D
N
turnaround
USB interpacket delay (8 to 192 high-speed bit times)
Rev. 02 — 21 January 2009
link decision time (1 to 14 clocks)
IDLE
ULPI Hi-Speed USB transceiver
Figure
Section
19.
© ST-NXP Wireless 2009. All rights reserved.
11.5). When in
(one to two clocks)
TXCMD
TX start delay
ISP1705
SYNC
D0
004aaa713
41 of 89
D1