ISP1705AETTM STEricsson, ISP1705AETTM Datasheet - Page 16

• Manufacturer Part Number: ISP1705AETTM
• Manufacturer: STEricsson

Specifications of ISP1705AETTM

• Lead Free Status / RoHS Status: Compliant

ISP1705_2
Product data sheet
Fig 7.
DATA[7:0]
RESET_N
CLOCK
NXT
STP
DIR
Interface behavior with respect to RESET_N during normal mode
8.11.1 Interface protection
8.11.2 Interface behavior with respect to RESET_N during normal mode
(link must drive)
(link must drive)
By default, the ISP1705 enables a weak pull-up resistor on STP. If the STP pin is
unexpectedly HIGH at any time, the ISP1705 will protect the ULPI interface by enabling
weak pull-down resistors on DATA[7:0].
The interface protect feature prevents unwanted activity of the ISP1705 whenever the
ULPI interface is not correctly driven by the link. For example, when the link powers up
more slowly than the ISP1705.
The interface protect feature can be disabled by setting the INTF_PROT_DIS bit to
logic 1.
The use of the RESET_N pin is optional. When RESET_N is asserted (LOW), all logic in
the ISP1705 will be reset, including the analog circuitry and ULPI registers.
During reset, the link must pull down DATA[7:0] to 00h and drive STP to LOW for one
cycle before reset assertion until the next rising edge of the clock after reset deassertion,
otherwise undefined behavior may result. Ensure that there is no glitch or noise on
DATA[7:0] during reset. When RESET_N is deasserted (HIGH), a 60 MHz clock will start
and the link must operate the bus according to the ULPI bus protocol.
Figure 7
subsequently deasserted (HIGH). The behavior of
is asserted. If RESET_N is not used, it must be connected to V
shows the ULPI interface behavior when RESET_N is asserted (LOW), and
link pull down
Rev. 02 — 21 January 2009
Figure 7
ULPI Hi-Speed USB transceiver
applies only when chip select
CC(I/O)
© ST-NXP Wireless 2009. All rights reserved.
.
ISP1705
004aab065
15 of 89