ISP1705AETTM STEricsson, ISP1705AETTM Datasheet - Page 28

• Manufacturer Part Number: ISP1705AETTM
• Manufacturer: STEricsson

Specifications of ISP1705AETTM

• Lead Free Status / RoHS Status: Compliant

ISP1705_2
Product data sheet
After the register configuration is complete:
By default, the clock is powered down when the ISP1705 enters UART mode. If the link
requires CLOCK to be running in UART mode, it can set the CLOCK_SUSPENDM bit in
the INTF_CTRL register (see
Transparent UART mode is exited by asserting the STP pin to HIGH or by toggling chip
select.
The INT pin is asserted and latched whenever an unmasked interrupt event occurs. When
the link detects INT as HIGH, it must wake up the PHY from transparent UART mode by
asserting STP. When the PHY is in synchronous mode, the link can read the
USB_INTR_L register (see
that the ISP1705 does not implement the optional Carkit Interrupt registers.
An alternative way to exit UART mode is to set chip select to non-active for more than
t
be put in default synchronous mode.
PWRDN
1. Set the XCVRSELECT[1:0] bits in the FUNC_CTRL register (see
2. Set the DP_PULLDOWN and DM_PULLDOWN bits in the OTG_CTRL register (see
3. Set the TERMSELECT bit in the FUNC_CTRL register (see
4. Set the TXD_EN and RXD_EN bits in the CARKIT_CTRL register (see
5. Set the CARKIT_MODE bit in the INTF_CTRL register (see
1. A weak pull-up resistor will be enabled on the DP and DATA0 pins. This is to avoid the
2. The 39
3. One clock cycle after DIR goes from LOW to HIGH, the ISP1705 will drive the data
4. UART buffers between DATA0 or DATA1 and DM or DP are enabled. Transparent
(low speed) or 01b (full speed). This setting affects the rise time and the fall time of
the UART transmitting signal on the DM line.
Section
(power-on default value).
Remark: Mandatory when a full-speed driver is used and optional for a low-speed
driver.
to logic 1. These two bits must be set together in one TXCMD.
Remark: The CARKIT_MODE, TXD_EN and RXD_EN bits must be set to logic 1.
The sequence of setting these register bits is ignored.
possible floating condition on these input pins when UART mode is enabled.
bus for five clock cycles. This is to charge the DATA0 pin to a HIGH level for a slow
link. However, the link can start driving DATA0 to HIGH immediately after the
turnaround cycle.
UART mode is entered.
Remark: The DP pin will be slowly charged up to HIGH by the weak pull-up resistor.
The time needed depends on the capacitive loading on DP.
and then set it to active. A power-on reset will be generated and the ULPI bus will
11.7) to logic 0.
serial termination resistors on the DP and DM pins will be enabled.
Rev. 02 — 21 January 2009
Section
Section
11.11) to determine the source of the interrupt. Note
11.6) to logic 1 before entering UART mode.
ULPI Hi-Speed USB transceiver
Section
Section
© ST-NXP Wireless 2009. All rights reserved.
Section
ISP1705
11.5) to logic 0
11.6) to logic 1.
Section
11.5) to 10b
11.14)
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