ISP1705AETTM STEricsson, ISP1705AETTM Datasheet - Page 87

• Manufacturer Part Number: ISP1705AETTM
• Manufacturer: STEricsson

Specifications of ISP1705AETTM

• Lead Free Status / RoHS Status: Compliant

24. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10. Interface behavior when entering UART mode . .28
Fig 11. Interface behavior when exiting UART mode . . .28
Fig 12. Single and back-to-back RXCMDs from the
Fig 13. RXCMD A_VBUS_VLD indicator source . . . . . . .34
Fig 14. Example of register write, register read, extended
Fig 15. USB reset and high-speed detection handshake
Fig 16. Example of using the ISP1705 to transmit and
Fig 17. High-speed transmit-to-transmit packet timing . .40
Fig 18. High-speed receive-to-transmit packet timing . . .41
Fig 19. Preamble sequence . . . . . . . . . . . . . . . . . . . . . . .42
Fig 20. Full speed suspend and resume . . . . . . . . . . . . .43
Fig 21. High speed suspend and resume . . . . . . . . . . . .45
Fig 22. Remote wake-up from low-power mode . . . . . . .47
Fig 23. Transmitting USB packets without automatic SYNC
Fig 24. Example of transmit followed by receive in 6-pin
Fig 25. Example of transmit followed by receive in 3-pin
Fig 26. Rise time and fall time . . . . . . . . . . . . . . . . . . . . .72
Fig 27. Timing of TX_DAT and TX_SE0 to DP and DM. .72
Fig 28. Timing of TX_ENABLE to DP and DM. . . . . . . . .72
Fig 29. Timing of DP and DM to RX_RCV, RX_DP and
Fig 30. ULPI timing interface . . . . . . . . . . . . . . . . . . . . . .73
Fig 31. ISP1705 in peripheral-only application . . . . . . . .74
Fig 32. ISP1705 in OTG application . . . . . . . . . . . . . . . .75
Fig 33. ISP1705 in host application . . . . . . . . . . . . . . . . .76
Fig 34. Package outline SOT818-1 (HVQFN36) . . . . . . .77
Fig 35. Package outline SOT912-1 (TFBGA36) . . . . . . .78
Fig 36. Temperature profiles for large and small
ISP1705_2
Product data sheet
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Pin configuration HVQFN36 . . . . . . . . . . . . . . . . .5
Pin configuration TFBGA36 . . . . . . . . . . . . . . . . . .5
Digital overcurrent detection scheme. . . . . . . . . .12
Internal power-on reset timing . . . . . . . . . . . . . . .13
Power-up and reset sequence required before the
ULPI bus is ready for use . . . . . . . . . . . . . . . . . .14
Interface behavior with respect to RESET_N during
normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Interface behavior with respect to chip select . . .16
V
ISP1705 to the link. . . . . . . . . . . . . . . . . . . . . . . .32
register write and extended register read . . . . . .36
(chirp) sequence . . . . . . . . . . . . . . . . . . . . . . . . .38
receive USB data . . . . . . . . . . . . . . . . . . . . . . . . .39
and EOP generation . . . . . . . . . . . . . . . . . . . . . .48
serial mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
serial mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
RX_DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
BUS
pin internal pull-up and pull-down scheme .19
Rev. 02 — 21 January 2009
ULPI Hi-Speed USB transceiver
© ST-NXP Wireless 2009. All rights reserved.
ISP1705
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