MC33910G5AC Freescale, MC33910G5AC Datasheet - Page 43

• Manufacturer Part Number: MC33910G5AC
• Manufacturer: Freescale

Specifications of MC33910G5AC

• Turn Off Delay Time: 10us
• Number Of Drivers: 2
• Operating Temperature (min): -40C
• Operating Temperature (max): 125C
• Operating Temperature Classification: Automotive
• Lead Free Status / RoHS Status: Compliant

Table 23. Cyclic Sense and Force Wake-up Interval
Watchdog Status Register - WDSR
is also returned when writing to the TIMCR.
WDTO - Watchdog Timeout
either a watchdog timeout or by an attempt to clear the
Watchdog within the window closed.
(TIMCR) will clear the WDTO bit.
WDERR - Watchdog Error
watchdog resistor. In this condition the watchdog is using the
internal, lower precision timebase. The Windowing function is
disabled.
WDOFF - Watchdog Off
to Ground and therefore disabled. In this case watchdog
CYSX8
Notes
Analog Integrated Circuit Device Data
Freescale Semiconductor
66.
67.
This register returns the Watchdog status information and
This read-only bit signals the last reset was caused by
Any access to this register or the Timing Control Register
1 = Last reset caused by watchdog timeout
0 = None
This read-only bit signals the detection of a missing
1 = WDCONF pin resistor missing
0 = WDCONF pin resistor not floating
This read-only bit signals that the watchdog pin connected
X
0
0
0
0
0
0
0
1
1
1
1
1
1
1
bit CYSX8 is located in Configuration Register (CFR)
No Cyclic Sense and no Force Wake-up available.
(66)
Table 24. Watchdog Status Register - $A/$B
Read
CYST2
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
WDTO
S3
CYST1
0
0
1
1
0
0
1
1
0
1
1
0
0
1
1
WDERR
S2
CYST0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
WDOFF
S1
No cyclic sense
WDWO
1120 ms
Interval
S0
100 ms
120 ms
140 ms
160 ms
320 ms
480 ms
640 ms
800 ms
960 ms
20 ms
40 ms
60 ms
80 ms
(67)
timeouts are disabled and the device automatically enters
Normal mode out of Reset. This might be necessary for
software debugging and for programming the Flash memory.
WDWO - Watchdog Window Open
open for clears. The purpose of this bit is for testing. Should
be ignored in case WDERR is High.
Analog Multiplexer Control Register - MUXCR
the divider ration for the L1 input divider.
L1DS - L1 Analog Input Divider Select
analog input. Voltage is internally clamped to VDD.
MXx - Analog Multiplexer Input Select
multiplexed to the ADOUT0 pin according to
buffer is not powered and the ADOUT0 output is left floating
to achieve lower current consumption.
Table 26. Analog Multiplexer Channel Select
MX2
1 = Watchdog is disabled
0 = Watchdog is enabled
This read-only bit signals when the watchdog window is
1 = Watchdog window open
0 = Watchdog window closed
This register controls the analog multiplexer and selects
This write-only bit selects the resistor divider for the L1
0 = L1 Analog divider: 1
1 = L1 Analog divider: 3.6 (typ.)
These write-only bits selects which analog input is
When disabled or when in Stop or Sleep mode, the output
0
0
0
0
1
1
1
1
Table 25. Analog Multiplexer Control Register -$C
Condition
Reset
Value
Reset
Write
MX1
0
0
1
1
0
0
1
1
L1DS
POR
C3
1
MX0
0
1
0
1
0
1
0
1
LOGIC COMMANDS AND REGISTERS
FUNCTIONAL DEVICE OPERATIONS
POR, Reset mode or ext_reset
MX2
C2
0
Die Temperature Sensor
VSENSE input
MX1
C1
0
Reserved
Reserved
Reserved
Reserved
Meaning
Disabled
L1 input
Table
MX0
C0
0
26.
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