M36W0R5040B7ZAQF Micron Technology Inc, M36W0R5040B7ZAQF Datasheet - Page 12
M36W0R5040B7ZAQF
Manufacturer Part Number
M36W0R5040B7ZAQF
Description
Manufacturer
Micron Technology Inc
Datasheet
1.M36W0R5040B7ZAQF.pdf
(24 pages)
Specifications of M36W0R5040B7ZAQF
Operating Supply Voltage (max)
1.95V
Operating Temperature (max)
85C
Mounting
Surface Mount
Lead Free Status / RoHS Status
Supplier Unconfirmed
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Signal descriptions
2.12
2.13
2.14
2.15
2.16
2.17
2.18
12/24
PSRAM Output Enable (G
The Output Enable, G
cycles to be achieved with the common I/O data bus.
PSRAM Write Enable (W
The Write Enable, W
PSRAM Upper Byte Enable (UB
The Upper Byte Enable, UB
DQ15) to or from the upper part of the selected address during a write or read operation.
PSRAM Lower Byte Enable (LB
The Lower Byte Enable, LB
DQ7) to or from the lower part of the selected address during a write or read operation.
V
V
main power supplies for all flash memory operations (read, program, and erase).
V
The V
the refresh logic, even when the device is not being accessed.
V
V
outputs to be powered independently of the flash memory and PSRAM core power supplies:
V
DDF
DDQ
DDF
DDF
DDP
DDQ
provides the power supply to the internal core of the flash memory component. It is the
and V
DDP
provides the power supply for the flash memory and PSRAM I/O pins. This allows all
supply voltage
supply voltage
supply voltage
supply voltage supplies the power for all operations (read or write) and for driving
DDP
, respectively.
P
P
, controls the bus write operation of the memory.
, provides a high speed tri-state control, allowing fast read/write
P
P
, gates the data on the lower byte data inputs/outputs (DQ0-
, gates the data on the upper byte data inputs/outputs (DQ8-
P
)
P
)
P
P
)
)
M36W0Rx0x0x7