PF38F1030W0YCQEA Micron Technology Inc, PF38F1030W0YCQEA Datasheet - Page 81

• Manufacturer Part Number: PF38F1030W0YCQEA
• Manufacturer: Micron Technology Inc

Specifications of PF38F1030W0YCQEA

• Operating Supply Voltage (max): 1.95V
• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Numonyx™ Wireless Flash Memory (W18)
Figure 38: Example: Latency Count Setting at 3
14.3
14.4
November 2007
Order Number: 290701-18
WAIT Signal Polarity (RCR[10])
If the WAIT bit is cleared (RCR[10]=0), then WAIT is configured to be asserted low.
This means that a 0 on the WAIT signal indicates that data is not ready and the data
bus contains invalid data. Conversely, if RCR[10] is set, then WAIT is asserted high. In
either case, if WAIT is deasserted, then data is ready and valid. WAIT is asserted during
asynchronous page mode reads.
WAIT Signal Function
The WAIT signal indicates data valid when the device is operating in synchronous mode
(RCR[15]=0), and when addressing a partition that is currently in read-array mode.
The WAIT signal is only “deasserted” when data is valid on the bus.
When the device is operating in synchronous non-read-array mode, such as read
status, read ID, or read query, WAIT is set to an “asserted” state as determined by
RCR[10]. See
Waveform” on page
When the device is operating in asynchronous page mode or asynchronous single word
read mode, WAIT is set to an “asserted” state as determined by RCR[10]. See
“Page-Mode Read Operation Waveform” on page
Operation Waveform” on page
From a system perspective, the WAIT signal is in the asserted state (based on
RCR[10]) when the device is operating in synchronous non-read-array mode (such as
Read ID, Read Query, or Read Status), or if the device is operating in asynchronous
mode (RCR[15]=1). In these cases, the system software should ignore (mask) the
WAIT signal, because it does not convey any useful information about the validity of
what is appearing on the data bus.
A
ADV# (V)
DQ
MAX-0
CE# (E)
CLK (C)
15-0
(A)
(D/Q)
Figure 12, “WAIT Signal in Synchronous Non-Read Array Operation
35.
t
ADD-DELAY
0st
Code 3
29.
1nd
R103
Valid Address
High Z
2rd
31, and
Figure 6, “Asynchronous Read
3th
t
DATA
4th
Output
Valid
Figure 8,
Datasheet
Output
Valid
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