RD28F1604C3B110 Intel, RD28F1604C3B110 Datasheet - Page 42

• Manufacturer Part Number: RD28F1604C3B110
• Manufacturer: Intel

Specifications of RD28F1604C3B110

• Operating Supply Voltage (max): 3.3V
• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

C3 SCSP Flash Memory
7.1.2
7.2
7.2.1
7.2.2
26 Aug 2005
42
C3 adds the following new features to Intel Advanced Boot Block architecture:
For more information on specific advantages of the C3, please see AP-658 Designing with the
Advanced+ Boot Block Flash Memory Architecture.
Flash Control Considerations
The flash device is protected against accidental block erasure or programming during power
transitions. Power supply sequencing is not required, since the device is indifferent as to which
power supply, F-VPP or F-VCC, powers-up first. Example flash power supply configurations are
shown in
F-RP# Connected to System Reset
The use of F-RP# during system reset is important with automated program/erase devices since the
system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs
without a flash memory reset, proper CPU initialization will not occur because the flash memory
may be providing status information instead of array data. Intel recommends connecting F-RP# to
the system CPU RESET# signal to allow proper CPU/flash initialization following system reset.
System designers must guard against spurious writes when F-V
both F-WE# and F-CE# must be low for a command write, driving either signal to V
writes to the device. The CUI architecture provides additional protection since alteration of
memory contents can only occur after successful completion of the two-step command sequences.
The device is also disabled until F-RP# is brought to V
inputs.
By holding the device in reset (F-RP# connected to system PowerGood) during power-up/down,
invalid bus conditions during power-up can be masked, providing yet another level of memory
protection.
F-V
The CUI latches commands as issued by system software and is not altered by F-V
transitions or WSM actions. Its default state upon power-up, after exit from reset mode or after
F-V
After any program or block erase operation is complete (even after F-V
V
flash memory array is desired.
C3 Flash Memory Features
•
•
•
•
PPLK
CC
Instant, individual block locking provides software/hardware controlled, independent locking/
unlocking of any block with zero latency to protect code and data.
A 128-bit Protection Register enables system security implementations.
Improved 12 V production programming simplifies the system configuration required to
implement 12 V fast programming.
Common Flash Interface (CFI) provides component information on the chip to allow software-
independent device upgrades.
CC
Intel
), the CUI must be reset to read array mode via the Read Array command if access to the
transitions above V
, F-V
Figure 12 “Example Power Supply Configurations” on page
®
Advanced+ Boot Block Flash Memory (C3) SCSP Family
PP
and F-RP# Transition
Order Number: 252636, Revision: 004
LKO
(Lockout voltage), is read array mode.
IH
, regardless of the state of its control
CC
voltages are above V
43.
PP
transitions down to
PP
IH
or F-CE#
Datasheet
will inhibit
LKO
. Since