M36W0R5040B7ZAQE Micron Technology Inc, M36W0R5040B7ZAQE Datasheet
M36W0R5040B7ZAQE
Specifications of M36W0R5040B7ZAQE
Related parts for M36W0R5040B7ZAQE
M36W0R5040B7ZAQE Summary of contents
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Mbits x 16, multiple bank, burst) flash memory and 8-Mbit (512 Kbit x16) or 16-Mbit (1 Mbit x 16) PSRAM MCP Features Multichip package – 1 die Mbits (2 or ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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M36W0Rx0x0x7 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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M36W0Rx0x0x7 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Description 1 Description The M36W0R5030x7, M36W0R5040x7, and M36W0R6040x7 combine two memory devices in a multichip package: a 32- or 64-Mbit, multiple bank flash memory, the M58WR032KT/B or M58WR064KT/B, respectively 16-Mbit PSRAM, the M69KB012AB or M69KB024AB, respectively. Recommended ...
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M36W0Rx0x0x7 Figure 1. Logic diagram 1. Amax is equal to A20 in the M36W0R50x0x7 and A21 in the M36W0R6040x7 DDQ PPF V DDF 22 (1) A0-Amax M36W0R5030x7 F M36W0R5040x7 ...
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Description Table 2. Signal names Name A0-A18 DQ0-DQ15 V DDF V DDQ V PPF CCP NC DU Flash memory control functions A19-A20, A20, or (2) A20-A21 WAIT F W ...
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M36W0Rx0x0x7 Figure 2. TFBGA connections (top view through package ...
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Signal descriptions 2 Signal descriptions See Figure 1: Logic diagram connected to this device. 2.1 Address inputs (A0-A21) Addresses A0-A18 are common inputs for the flash memory and PSRAM components. The address inputs select the cells in the memory array ...
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M36W0Rx0x0x7 2.6 Flash Write Protect (WP Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is Low, V blocks cannot be changed. When Write Protect is at High, V the locked-down blocks ...
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Signal descriptions 2.12 PSRAM Output Enable (G The Output Enable, G cycles to be achieved with the common I/O data bus. 2.13 PSRAM Write Enable (W The Write Enable, W 2.14 PSRAM Upper Byte Enable (UB The Upper Byte Enable, ...
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M36W0Rx0x0x7 2.19 V program supply voltage PPF V is both a flash memory control input and a flash memory power supply pin. The two PPF functions are selected by the voltage range applied to the pin kept ...
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Functional description 3 Functional description The flash memory and PSRAM components have separate power supplies but share the same grounds. They are distinguished by two Chip Enable inputs: E and E for the PSRAM. P Recommended operating conditions do not ...
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M36W0Rx0x0x7 Figure 3. Functional block diagram A19-20 (1) or A20 (2) or A20-A21 A0-A18 (1) (2)(3) or A0-A19 1. Address inputs corresponding to the M36W0R5030x7 devices. 2. Address inputs corresponding to the M36W0R5040x7 devices. 3. Address inputs corresponding to the ...
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Functional description Table 3. Main operating modes Operation Flash read Flash write Flash address latch Flash output ...
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M36W0Rx0x0x7 4 Maximum ratings Stressing the device above the rating listed in cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating ...
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DC and AC parameters 5 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables in this section are derived from ...
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M36W0Rx0x0x7 Figure 5. AC measurement load circuit Table 6. Device capacitance Symbol C Input capacitance IN C Output capacitance OUT 1. Sampled only, not 100% tested. Please refer to the M58WR032KT/B and M58WR064KT/B and M69KB012AB or M69KB024AB datasheets for further ...
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Package mechanical 6 Package mechanical To meet environmental requirements, Numonyx offers the M36W0R50x0x7 and M36W0R6040x7 in RoHS compliant packages, which have a lead-free second-level interconnect. In compliance with JEDEC standard JESD97, the category of second-level interconnect is marked on the ...
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M36W0Rx0x0x7 Table 7. Stacked TFBGA88 ball array, 0.8 mm pitch, package mechanical data Symbol ddd E 10.000 FE1 SD SE Millimeters ...
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Part numbering 7 Part numbering Table 8. Ordering information scheme Example: Device type M36 = multichip package (multiple flash + RAM) Flash 1 architecture W = multiple bank, burst mode Flash 2 architecture 0 = none present Operating voltage R ...
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M36W0Rx0x0x7 8 Revision history Table 9. Document revision history Date Version 30-Jun-2008 29-Sep-2008 31-Mar-2009 Revision Details 1 Initial release. 2 Change from T=-30°C to T=-40°C. Replaced references to ECOPACK with RoHS compliant. 3 Changed footnote 1 in figure1. Revision history ...
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE ...