MT48LC16M16A2P-75:D Micron Technology Inc, MT48LC16M16A2P-75:D Datasheet - Page 41

• Manufacturer Part Number: MT48LC16M16A2P-75:D
• Description: IC, SDRAM, 256MBIT, 133MHZ, TSOP-54
• Manufacturer: Micron Technology Inc
• Type: SDRAMr
• Series: -r

Specifications of MT48LC16M16A2P-75:D

• Organization: 16Mx16
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 135mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Memory Type: DRAM - Sychronous
• Memory Configuration: 16 X 16
• Access Time: 5.4ns
• Page Size: 256Mbit
• Memory Case Style: TSOP
• No. Of Pins: 54
• Operating Temperature Range: 0°C To +70°C
• Format - Memory: RAM
• Memory Size: 256M (16Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-TSOP (0.400", 10.16mm Width)
• Lead Free Status / RoHS Status: Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
10. For a READ without auto precharge interrupted by a READ (with or without auto pre-
11. For a READ without auto precharge interrupted by a WRITE (with or without auto pre-
12. For a WRITE without auto precharge interrupted by a READ (with or without auto pre-
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto pre-
14. For a READ with auto precharge interrupted by a READ (with or without auto pre-
15. For a READ with auto precharge interrupted by a WRITE (with or without auto pre-
16. For a WRITE with auto precharge interrupted by a READ (with or without auto pre-
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto pre-
4. AUTO REFRESH, SELF REFRESH, and LOAD MODE REGISTER commands can only be is-
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command/Action column include READs or
8. Concurrent auto precharge: Bank n will initiate the auto precharge command when its
9. The burst in bank n continues as initiated.
Read with auto precharge enabled: Starts with registration of a READ command
with auto precharge enabled and ends when
bank will be in the idle state.
Write with auto precharge enabled: Starts with registration of a WRITE command
with auto precharge enabled and ends when
bank will be in the idle state.
sued when all banks are idle.
represented by the current state only.
WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.
burst has been interrupted by bank m burst.
charge), the READ to bank m will interrupt the READ on bank n, CAS latency (CL) later.
charge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM
should be used one clock prior to the WRITE command to prevent bus contention.
charge), the READ to bank m will interrupt the WRITE on bank n when registered, with
the data-out appearing CL later. The last valid WRITE to bank n will be data-in regis-
tered one clock prior to the READ to bank m.
charge), the WRITE to bank m will interrupt the WRITE on bank n when registered. The
last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank
m.
charge), the READ to bank m will interrupt the READ on bank n, CL later. The PRE-
CHARGE to bank n will begin when the READ to bank m is registered.
charge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM
should be used two clocks prior to the WRITE command to prevent bus contention. The
PRECHARGE to bank n will begin when the WRITE to bank m is registered.
charge), the READ to bank m will interrupt the WRITE on bank n when registered, with
the data-out appearing CL later. The PRECHARGE to bank n will begin after
where
will be data-in registered one clock prior to the READ to bank m.
charge), the WRITE to bank m will interrupt the WRITE on bank n when registered. The
PRECHARGE to bank n will begin after
to bank m is registered. The last valid WRITE to bank n will be data registered one clock
to the WRITE to bank m.
t
WR begins when the READ to bank m is registered. The last valid WRITE bank n
41
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
WR is met, where
t
t
RP has been met. After
RP has been met. After
256Mb: x4, x8, x16 SDRAM
t
WR begins when the WRITE
© 1999 Micron Technology, Inc. All rights reserved.
t
t
RP is met, the
Truth Tables
RP is met, the
t
WR is met,