MT49H64M9CHT-25:A Micron Technology Inc, MT49H64M9CHT-25:A Datasheet
MT49H64M9CHT-25:A
Specifications of MT49H64M9CHT-25:A
Related parts for MT49H64M9CHT-25:A
MT49H64M9CHT-25:A Summary of contents
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... Vext, 1.8V Vdd, 1.5V or 1.8V Vddq I/O • On-die termination (ODT) Rtt PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_D1.fm - Rev. F 6/09 EN Products and specifications discussed herein are subject to change by Micron without notice. 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II ® II Options • Clock cycle timing – ...
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... Due to space limitations, BGA-packaged components have an abbreviated part marking that is different from the part number. Micron’s BGA Part Marking Decoder is available on Micron’s Web site at www.micron.com. PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_D1.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II Example Part Number: MT49H32M18CFM-25 :A MT49H Configuration I/O ...
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... Performing a TAP RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 TAP Registers .68 TAP Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIOTOC.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II Micron Technology, Inc., reserves the right to change products or specifications without notice. 3 Table of Contents ©2004 Micron Technology, Inc. All rights reserved. ...
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... List of Figures Figure 1: 576Mb RLDRAM II SIO Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Figure 2: State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Figure 3: Functional Block Diagram – 64 Meg Figure 4: Functional Block Diagram – 32 Meg x 18 Figure 5: 144-Ball µBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Figure 6: 144-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Figure 7: Clock Input . Figure 8: Nominal AS/ CS/ DS and Figure 9: Example Temperature Test Point Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Figure 10: Mode Register Set ...
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... Instruction Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Table 29: Boundary Scan (Exit) Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIOLOT.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II Micron Technology, Inc., reserves the right to change products or specifications without notice. 5 List of Tables ©2004 Micron Technology, Inc. All rights reserved. ...
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... Read and write accesses to the RLDRAM are burst-oriented. The burst length (BL) is programmable from setting the mode register. The device is supplied with 2.5V and 1.8V for the core and 1.5V or 1.8V for the output drivers ...
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... Figure 2: State Diagram WRITE MRS PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_D2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II Initialization sequence DSEL/NOP Automatic sequence Command sequence Micron Technology, Inc., reserves the right to change products or specifications without notice. 7 General Description READ AREF © ...
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Functional Block Diagrams Figure 3: Functional Block Diagram – 64 Meg ODT control CK CK# Control CS# logic REF# WE# Refresh 14 counter Mode register Row- address MUX A0–A21 Address 25 BA0–BA2 register 3 ...
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Figure 4: Functional Block Diagram – 32 Meg ODT control CK CK# Control CS# logic REF# WE# Refresh 14 counter Mode register Row- address MUX A0–A20 Address 24 BA0–BA2 register ...
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... Do not use. This signal is internally connected and has parasitic characteristics of an I/O. This may be optionally connected to GND. Note that if ODT is enabled, these pins will be con- nected to Vtt. PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_D2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM Vss ...
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... This may be optionally connected to GND function. This signal is internally connected and has parasitic characteristics of a clock input signal. This may be optionally connected to GND. PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_D2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II Ball Assignments and Descriptions ...
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... QK. Output data clocks: QKx and QKx# are opposite polarity, output data clocks. They are free-running, and during READs, edge-aligned with data output from the RLDRAM. QKx# is ideally 180 degrees out of phase with QKx. For the x9 device, all Qs are aligned with QK0 and QK0#. For the x18 device, QK0 and QK0# are aligned with Q0– ...
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... NF – PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_D2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II Reserved for future use: This signal is not connected and may be connected to ground. Do not use: These balls may be connected to ground. Note that if ODT is enabled, these pins will be connected to Vtt. ...
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... Pb, 2% Ag) or SAC305 (96.5% Sn, 3% Ag, 0.5% Cu). Dimensions apply solder balls post-reflow on Ø0.4 SMD ball pads. 17 CTR 1 TYP 0.8 TYP 11 ±0.15 PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_D2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II 10º TYP 0.68 ±0.1 Ball 18.5 ± ...
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... SAC305 (96.5% Sn, 3% Ag, 0.5% Cu). Dimensions apply solder balls post-reflow on Ø0.39 SMD ball pads. 17 CTR 1 TYP Notes: 1. All dimensions are in millimeters. PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_D2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II 10º TYP 0.73 ±0.1 Ball 18.5 ± ...
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... Ball A12 17.00 8.50 4.40 11.00 ±0.10 Notes: 1. All dimensions are in millimeters. PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_D2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II 0.75 ±0.05 8.80 Ball A1 Ball A1 ID 9.25 ±0. 18.50 ±0.10 1.00 TYP C L 5.50 ± ...
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... Vdd ≤ +1.9V, +2.38V ≤ Vext ≤ +2.63V, +1.4V ≤ Vddq ≤ Vdd, Vref = Vddq/ Input slew rate is specified in Table 7 on page 20. PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_D2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II Isb1 (Vdd) x9/x18 Isb1 (Vext) Isb2 (Vdd) x9/x18 Isb2 (Vext) Idd1 (Vdd) x9/x18 Idd1 (Vext) ...
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... Vih(AC). PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_D2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II every half clock cycle (twice per clock). LOW every clock cycle (once per clock). mand access. For this is every clock, for this is every other clock, and for this is every fourth clock ...
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... DC value. Thus, from Vddq/2, Vref is allowed ±2% Vddq/2 for DC error and an addi- tional ±2% Vddq/2 for AC noise. This measurement taken at the nearest Vref bypass capacitor. PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II Electrical Specifications – AC and DC Conditions Symbol – ...
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... IOL flows into the device. 10. If MRS bit use RQ = 250Ω in the equation in lieu of presence of an external imped- ance matched resistor. 11. For Vol and Voh, refer to the RLDRAM II HSPICE or IBIS driver models. Table 7: Input AC Logic Levels Unless otherwise noted: +0°C ≤ T ...
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... CK and CK# must meet at least Vid(DC) MIN when static and centered around Vddq/2. 3. Minimum peak-to-peak swing violation to tri-state CK and CK# after the part is initialized. PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II Electrical Specifications – AC and DC Symbol Min Vin(DC) – ...
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... The above descriptions also pertain to data setup and hold derating when CK/CK# are replaced with DK/DK#. PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II Electrical Specifications – AC and specifications when the slew rate of any of these input signals is less than ...
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... PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II Electrical Specifications – AC and AS/ CS Vih(AC Min to CK/CK# AH/ CH CK/CK# Crossing Crossing to Vref CK, CK# Differential Slew Rate: 2.0 V/ns – ...
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... PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II Electrical Specifications – AC and Vih(AC) Min t to CK/CK# DH CK/CK# Crossing Crossing to Vref DK, DK# Differential Slew Rate: 2.0 V/ns – ...
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... Input/output capacitance (D, Q, DM, and QK/QK#) Clock capacitance (CK/CK#, and DK/DK#) JTAG pins Notes: 1. Capacitance is not tested on ZQ pin. 2. JTAG pins are tested at 50 MHz. PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM and AH/ CH/ ...
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... QK edge to output QKQ0, –0.12 t QKQ1 data edge t QKQ –0.22 QK edge to any output data edge PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II -18 -25E Max Min Max 2.7 2.5 5 100 –150 ...
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... DVW QHP - t ( QKQx [MAX QKQx [MIN]|) Refresh t Average periodic REFI refresh interval PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II -18 -25E Max Min Max 0.22 –0.3 0.3 t – QHP - – QKQx [MAX] + [MAX] + ...
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... To improve efficiency, eight AREF commands (one for each bank) can be posted to the RLDRAM on consecutive cycles at periodic intervals of 1.95µs. PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II Electrical Specifications – AC and DC Vtt 50Ω ...
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... Table 14. For designs that are expected to last several years and require the flexi- bility to use several DRAM die shrinks, consider using final target theta values (rather than existing values) to account for increased thermal impedances from the die size reduction. The RLDRAM device’ ...
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... Figure 9: Example Temperature Test Point Location Test point PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II Temperature and Thermal Impedance 18.50 9.25 5.50 11.00 Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... Description of Commands Command DSEL/NOP The NOP command is used to perform a no operation to the RLDRAM, which essentially deselects the chip. Use the NOP command to prevent unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. Output values depend on command history. ...
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... During an MRS command, the address inputs A0–A17 are sampled and stored in the mode register. After issuing a valid MRS command, command can be issued to the RLDRAM. This statement does not apply to the consecu- tive MRS commands needed for internal logic reset during the initialization routine. The MRS command can only be issued when all banks are idle and no bursts are in progress ...
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... A10–A17 must be set to zero; A18–An = “Don’t Care.” not used in MRS not available. 4. DLL RESET turns the DLL off. 5. Available in 576Mb part only. 6. ±30% temperature variation. PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II A17 A10 ...
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... Burst Length (BL) Burst length is defined by M3 and M4 of the mode register. Read and write accesses to the RLDRAM are burst-oriented, with the burst length being programmable Figure 12 on page 35 illustrates the different burst lengths with respect to a READ command. Changes in the burst length affect the width of the address bus (see Table 19 on page 35 for details) ...
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... DRAM. In multiplexed address mode, the address can be provided to the RLDRAM in two parts that are latched into the memory with two consecutive rising clock edges. This provides the advantage of only needing a maximum of 11 address balls to control the RLDRAM, reducing the number of signals on the controller side ...
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... ODT. The ODT function is dynamically switched off when a Q begins to drive after a READ command is issued. Similarly, ODT is designed to switch on at the Qs after the RLDRAM has issued the last piece of data. The D and DM pins will always be terminated. See section entitled "Operations" on page 41 for relevant timing diagrams. ...
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... Vtt is expected to be set equal to Vref and must track variations in the DC level of Vref. 3. The Rtt value is measured at 95°C T Figure 13: On-Die Termination-Equivalent Circuit D PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II Symbol Min Vtt 0.95 × Vref 1.05 × Vref Rtt 125 ...
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... WRITE command. During WRITE commands, data will be registered at both edges of DK according to the programmed burst length (BL). The RLDRAM operates with a WRITE latency (WL) that is one cycle longer than the programmed READ latency (RL + 1), with the first valid data registered at the first rising DK edge WL cycles after the WRITE command ...
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... CS# WE# REF# ADDRESS BANK ADDRESS PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II t QKQ0 is referenced to Q0–Q8). t QKQx is derived at each QKx clock edge and is not cumulative over time QKQ [MAX QKQ [MIN]|). See Figure 29 on page 52 for illustration. ...
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... RLDRAM requires 128K cycles at an average periodic interval of 0.24µs MAX (actual periodic refresh interval is 32ms/16K rows/8 = 0.244µs). To improve efficiency, eight AREF commands (one for each bank) can be posted to the RLDRAM at periodic intervals of 1.95µs (32ms/16K rows = 1.95µs). Figure 30 on page 53 illustrates an example of a refresh sequence ...
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... HIGH until Vdd is at the same level as Vddq. Care should be taken to avoid bus conflicts during this period Vid(DC) on CK/CK# can not be met prior to being applied to the RLDRAM, placing a large external resistor from CS# to Vdd is a viable option for ensuring the command bus does not receive unwanted commands during this unspecified state ...
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... The sequence of the eight AUTO REFRESH commands (with respect to the 1,024 NOP com- mands) does not matter required for any operation, tRC must be met between an AUTO REFRESH command and a subsequent VALID command to the same bank. PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM ...
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... The sequence of the eight AUTO REFRESH commands (with respect to the 1,024 NOP com- mands) does not matter required for any operation, AUTO REFRESH command and a subsequent VALID command to the same bank. PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II V and V ramp DD, ...
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... WL - CKDK (MIN) DK CKDK (MAX) DK Notes data-in for address n; subsequent elements of burst are applied following DI an PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM NOP NOP CKDK t CKDK 44 T6 T6n T4 T5 T5n NOP NOP NOP ...
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... Each WRITE command may be to any bank; if the second WRITE is to the same bank must be met. 5. Nominal conditions are assumed for specifications not defined. PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM WRITE NOP WRITE ...
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... data-out from bank b and address n. 3. Three subsequent elements of each burst follow DI an and DO bn Nominal conditions are assumed for specifications not defined. PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM NOP NOP NOP ...
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... Add n DK Notes data-in from address n. 2. Subsequent elements of burst are provided on following clock edges Nominal conditions are assumed for specifications not defined. PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM NOP NOP NOP ...
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... CKQK (MAX) QK# QK QVLD Q Notes data-out from address n. 2. Three subsequent elements of the burst are applied following Nominal conditions are assumed for specifications not defined. PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM NOP NOP ...
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... Bank address can be to any bank, but the subsequent READ can only be to the same bank has been met. 6. Data from the READ commands to banks c and d will appear on subsequent clock cycles that are not shown. PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM READ READ READ ...
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... data-in for bank x and address n. 3. Three subsequent elements of each burst follow each DI xn and DO xn Nominal conditions are assumed for specifications not defined. PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM T4n NOP ...
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... QKQ0 is referenced to Q0–Q8. 3. Minimum data valid window ( t QHP - ( PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II t QHP 1 t QHP 1 t QKQ0 (MAX QKQ0 (MAX QKQ0 (MIN QKQ0 (MIN DVW 3 t DVW 3 ...
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... QKQ1 is referenced to Q9–Q17 QKQ takes into account the skew between any QKx and any Q. PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II QK0# QK0 t QHP 1 t QKQ0 (MAX QKQ0 (MAX QKQ0 (MAX QKQ0 (MIN) 3 ...
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... BANK DK, DK# DM Notes: 1. AREFx = AUTO REFRESH command to bank x. 2. ACx = any command to bank x; ACy = any command to bank y. 3. BAx = bank address to bank x; BAy = bank address to bank y. PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM CK ...
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... QVLD Q Q ODT Notes data out followed by the remaining bits of the burst. 3. Nominal conditions are assumed for specifications not defined. PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM NOP NOP NOP Q ODT on Q ODT on ...
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... data-out from bank a and address data-in for bank b and address Three subsequent elements of each burst appear after each DO an and DI bn. 4. Nominal conditions are assumed for specifications not defined. PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM READ NOP ...
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... BANK BA ADDRESS Notes: 1. The minimum setup and hold times of the two address parts are defined PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II WRITE Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... Address A5 must be set HIGH. This and the following step set the desired mode register once the RLDRAM is in multiplexed address mode. 5. Any command or address. 6. The above sequence must be followed in order to power up the RLDRAM in the multiplexed address mode. 7. DLL must be reset and CK# must separated at all times to prevent bogus commands from being issued. ...
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... BA0–BA2 are “Don’t Care.” 8. Addresses A0, A3, A4, A5, A8, and A9 must be set as shown in order to activate the mode register in the multiplexed address mode. PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II A18 . . . A10 A9 A8 ...
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... Address Mapping in Multiplexed Address Mode Table 21: Address Mapping in Multiplexed Address Mode Data Burst Width Length Ball A20 A20 x18 A20 Notes “Don’t Care.” PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II Address A21 ...
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... Configuration Tables in Multiplexed Address Mode In multiplexed address mode, the read and write latencies are increased by one clock cycle. However, the RLDRAM cycle time remains the same as when in non-multiplexed address mode. Table 22: Cycle Time and READ/WRITE Latency Configuration Table in Multiplexed Mode Notes 1–2 apply to the entire table ...
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... Three subsequent elements of the burst are applied following DI for each bank. 4. Each WRITE command may be to any bank; if the second WRITE is to the same bank, must be met. PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM ...
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... Nominal conditions are assumed for specifications not defined. 6. Bank address can be to any bank, but the subsequent READ can only be to the same bank has been met. PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM READ NOP ...
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... Bank address can be to any bank, but the subsequent READ can only be to the same bank has been met. 7. Data from the READ commands to banks b through bank d will appear on subsequent clock cycles (not shown). PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM NOP READ NOP ...
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... Three subsequent elements of the burst which appear following DI bn are not all shown. 7. Bank address can be to any bank, but the WRITE command can only be to the same bank has been met. PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM WRITE NOP ...
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... M8 needs to be set to 0 until the JTAG testing of the pin is complete. Note that upon power up, the default state of MRS bit M8 is low. If the RLDRAM boundary scan register used upon power up and prior to the initialization of the RLDRAM device imperative that the CK and CK# pins meet Vid(DC) or CS# be held HIGH from power up until testing ...
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... PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II IEEE 1149.1 Serial Boundary Scan (JTAG) Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... Run-test/ 0 Figure 43: TAP Controller Block Diagram TDI TCK TMS Notes 112 for all configurations. PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II IEEE 1149.1 Serial Boundary Scan (JTAG) reset Select Idle DR-scan 0 1 Capture-DR ...
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... Table 29 on page 73 shows the order in which the bits are connected. Each bit corre- sponds to one of the balls on the RLDRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the capture-DR state when the IDCODE command is loaded in the instruction register ...
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... The user must be aware that the TAP controller clock can only operate at a frequency MHz, while the RLDRAM clock operates significantly faster. Because there is a large difference between the clock frequencies possible that during the capture-DR state, an input or output will undergo a transition ...
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... T12 TCK TMS TDI TAP CONTROLLER Select-DR- Exit 2-IR Update-IR STATE TDO PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II IEEE 1149.1 Serial Boundary Scan (JTAG Select-DR- Select-IR- Capture-IR SCAN SCAN T13 T14 T15 ...
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... TMS setup Capture setup Hold times TMS hold Capture hold t Notes and ary scan register. PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II IEEE 1149.1 Serial Boundary Scan (JTAG (TCK THTL TLTH t MVTH t THMX (TMS) ...
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... Scan Register Sizes Register Name Instruction Bypass ID Boundary scan PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II IEEE 1149.1 Serial Boundary Scan (JTAG) Condition Symbol Vih Vil 0V ≤ Vin ≤ Vdd ILi Output disabled, ILo 0V ≤ ...
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... U11 PDF: 09005aef815b2df8/Source: 09005aef811ba111 576Mb_RLDRAM_II_SIO_Core2.fm - Rev. F 6/09 EN 576Mb: x9, x18 2.5V Vext, 1.8V Vdd, HSTL, SIO, RLDRAM II IEEE 1149.1 Serial Boundary Scan (JTAG) Description Captures I/O ring contents; Places the boundary scan register between TDI and TDO; This operation does not affect RLDRAM operations. ...
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... S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. RLDRAM is a trademark of Qimonda AG in various countries, and is used by Micron Technology, inc. under license from Qimonda. All other trademarks are the property of their respective owners. ...