M27W032-100M1 STMicroelectronics, M27W032-100M1 Datasheet - Page 9

• Manufacturer Part Number: M27W032-100M1
• Manufacturer: STMicroelectronics

Specifications of M27W032-100M1

• Density: 32Mb
• Organization: 2Mx16
• Interface Type: Parallel
• Bus Type: Parallel
• In System Programmable: External
• Access Time (max): 100ns
• Package Type: SO
• Reprogramming Technique: OTP
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 10mA
• Pin Count: 44
• Mounting: Surface Mount
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Supplier Unconfirmed

3. Finally, after all Words have been programmed,
The memory is now set to enter the Verify Phase.
Verify Phase. The Verify Phase is similar to the
Program Phase in that all Words must be resent to
the memory for them to be checked against the
programmed data.
Before any Bus Write Operation of the Verify
Phase, the Status Register must be read in order
to check that the PC is ready for the next operation
or if the reprogram of the location has failed (see
Table 6 and Figure 6).
Three successive steps are required to execute
the Verify Phase of the command:
1. The first Bus Write operation of the Verify Phase
2. Each subsequent Bus Write operation latches
Start Address), that indicates to the PC that the
Program Phase has to continue. A0 to A16 are
‘don’t care’.
a Bus Write operation (the (n+1)
Address, FA (A17 or a higher address pin
different from the Start Address), ends the
Program Phase.
latches the Start Address and the Word to be
verified.
the next Word to be verified and automatically
increments the internal Address Bus. As in the
Program Phase, it is not necessary to provide
the address of the location to be programmed
th
) with a Final
3. Finally, after all Words have been verified, a Bus
Exit Phase. After the Verify Phase ends, the Sta-
tus Register must be read to check if the command
has successfully completed or not (see Table 6
and Figure 6).
If the Verify Phase is successful, the memory re-
turns to Read mode and DQ6 stops toggling.
If the PC fails to reprogram a given location, the
Verify Phase terminates, DQ6 continues toggling
and error bit DQ5 is set in the Status Register. If
the error is due to a V
When the operation fails a Read/Reset command
must be issued to return the device to Read mode.
During the Multiple Word Program operation the
memory will ignore all commands. It is not possible
to issue any command to abort or pause the oper-
ation. Typical program times are given in Table 5.
Bus Read operations during the program opera-
tion will output the Status Register on the Data In-
puts/Outputs. See the section on the Status
Register for more details.
Note that the Multiple Word Program command
cannot change a bit set to ’0’ back to ’1’.
but only a Continue Address, CA (A17 to A20
equal to the Start Address).
Write cycle with a Final Address, FA (A17 or a
higher address pin different from the Start
Address) ends the Verify Phase.
PP
failure DQ4 is also set.
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