MT45W2MW16PGA-70 IT Micron Technology Inc, MT45W2MW16PGA-70 IT Datasheet
MT45W2MW16PGA-70 IT
Specifications of MT45W2MW16PGA-70 IT
Related parts for MT45W2MW16PGA-70 IT
MT45W2MW16PGA-70 IT Summary of contents
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... DQ11 A17 A7 DQ3 Vcc VccQ DQ12 NC A16 DQ4 Vss A15 DQ14 DQ13 A14 DQ5 DQ6 A13 DQ15 A19 A12 WE# DQ7 A18 A8 A9 A10 A11 A20 Top View (Ball Down) Part Number Example: MT45W2MW16PGA-70WT ©2007 Micron Technology, Inc. All rights reserved. Features ...
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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1: 48-Ball VFBGA Ball Assignment ...
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List of Tables Table 1: VFBGA Ball Descriptions ...
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General Description Micron for low-power, portable applications. The MT45W2MW16P is a 32Mb DRAM core device organized as 2 Meg x 16 bits. These devices include the industry-standard, asynchronous memory interface found on other low-power SRAM or pseudo-SRAM offerings. A user-accessible ...
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Ball Descriptions Table 1: VFBGA Ball Descriptions VFBGA Ball Assignment Symbol Type H6, G2, H1, D3, A[20:0] Input E4, F4, F3, G4, G3, H5, H4, H3, H2, D4, C4, C3, B4, B3, A5, A4 CE# Input A1 LB# ...
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Bus Operations Table 2: Bus Operations Mode Standby Read Write No operation PAR Partial-array refresh Deep power-down DPD Load configuration register Notes: 1. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When LB# alone is in ...
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Part-Numbering Information Micron CellularRAM devices are available in several different configurations and densi- ties (see Figure 3). Figure 3: Part Number Chart Micron Technology Product Family 45 = PSRAM/CellularRAM Memory Operating Core Voltage W = 1.7V–1.95V Address Locations M = ...
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Functional Description In general, the MT45W2MW16P device is a high-density alternative to SRAM and Pseudo SRAM products, popular in low-power, portable applications. The MT45W2MW16P contains a 33,554,432-bit DRAM core organized as 2,097,152 addresses by 16 bits. These devices include the ...
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Figure 5: READ Operation CE# OE# WE# ADDRESS DATA LB#/UB# Figure 6: WRITE Operation CE# OE# WE# ADDRESS DATA LB#/UB# PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 12/09 EN 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory ...
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Page Mode READ Operation Page mode is a performance-enhancing extension to the legacy asynchronous READ operation. In page-mode-capable products, an initial asynchronous read access is performed, then adjacent addresses can be quickly read by simply changing the low- order address. ...
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Low-Power Operation Standby Mode Operation During standby, the device current consumption is reduced to the level necessary to perform the DRAM REFRESH operation on the full array. Standby operation occurs when CE# and ZZ# are HIGH. The device will enter ...
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Figure 8: Software Access PAR Functionality NO Deep Power-Down Operation Deep power-down (DPD) operation disables all refresh-related activity. This mode is used when the system does not require the storage provided by the CellularRAM device. Any stored data will become ...
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Configuration Register Operation The configuration register (CR) defines how the CellularRAM device performs its trans- parent self refresh. Altering the refresh parameters can dramatically reduce current consumption during standby mode. Page mode control is also embedded into the CR. This ...
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Figure 10: Software Access Load Configuration Register ADDRESS CE# OE# WE# LB#/UB# DATA Figure 11: Software Access Read Configuration Register ADDRESS CE# OE# WE# LB#/UB# DATA PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 12/09 EN 32Mb: 2 Meg ...
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Figure 12: Configuration Register Bit Mapping All must be set to "0" CR[ Partial-Array Refresh (CR[2:0]) Default = Full-Array Refresh The PAR bits restrict REFRESH operation to a portion of the total memory array. This feature allows the ...
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Page Mode READ Operation (CR[7]) Default = Disabled The page mode operation bit determines whether page mode READ operations are enabled. In the power-up default state, page mode is disabled. Table 3: 32Mb Address Patterns for PAR (CR[ ...
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... Maximum and Typical Standby Currents The following table and figure refer to the maximum and typical standby currents for the MT45W2MW16PGA device. The typical values shown in Figure 13 on page 19 are measured with the default on-chip temperature sensor control enabled. Table 6: ...
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Figure 13: Typical Refresh Current vs. Temperature Table 7: Deep Power-Down Specifications and Conditions Description Deep power-down Table 8: Capacitance Specifications and Conditions Description Input capacitance Input/output capacitance (DQ) Notes: 1. These ...
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Figure 15: Output Load Circuit DUT Table 9: READ Cycle Timing Requirements Parameter Address access time Page access time LB#/UB# access time LB#/UB# disable to High-Z output LB#/UB# enable to Low-Z output Maximum CE# pulse width Chip select access time ...
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Table 10: WRITE Cycle Timing Requirements Parameter Address setup time Address valid to end of write Byte select to end of write CE# HIGH time during write Chip enable to end of write Data hold from write time Data write ...
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Timing Diagrams Figure 16: Power-Up Initialization Period Vcc, VccQ = 1.7V Table 13: Initialization Timing Parameters Parameter Initialization period (required before normal operations) Figure 17: Load Configuration Register ADDRESS CE# LB#/UB# WE# OE# ZZ# Figure 18: Deep Power-Down Entry and ...
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Figure 19: Single READ Operation (WE ADDRESS LB#/UB# DATA-OUT Figure 20: Page Mode READ Operation (WE ADDRESS A[20:4] ADDRESS A[3:0] LB#/UB# DATA-OUT PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 12/09 EN 32Mb: 2 Meg ...
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Figure 21: WRITE Cycle (WE# Control) ADDRESS LB#/UB# WE# DATA-IN DATA-OUT Figure 22: WRITE Cycle (CE# Control) ADDRESS LB#/UB# WE# DATA-IN DATA-OUT PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 12/09 EN 32Mb: 2 Meg x 16 Async/Page CellularRAM ...
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Figure 23: WRITE Cycle (LB#/UB# Control) ADDRESS LB#/UB# WE# DATA-IN DATA-OUT PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 12/09 EN 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory t WC Valid address CE# ...
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... All dimensions are in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 3. The MT45W2MW16PGA uses “green” packaging. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. CellularRAM is a trademark of Micron Technology, Inc ...