CY7C09359AV-9AC Cypress Semiconductor Corp, CY7C09359AV-9AC Datasheet - Page 15

• Manufacturer Part Number: CY7C09359AV-9AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09359AV-9AC

• Density: 144Kb
• Access Time (max): 9ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 40MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 13b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 230mA
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 18b
• Number Of Words: 8K
• Lead Free Status / RoHS Status: Not Compliant

Read/Write and Enable Operation
Address Counter Control Operation
Notes:
24. “X” = “Don’t Care,” “H” = V
25. ADS, CNTEN, CNTRST = “Don’t Care.”
26. OE is an asynchronous input signal.
27. When CE changes state In the pipelined mode, deselection and read happen in the following clock cycle.
28. CE
29. Data shown for flow-through mode; pipelined mode output will be delayed by one cycle.
30. Counter operation is independent of CE
Address
OE
A
H
X
X
X
X
X
X
L
n
0
and OE = V
Previous
Address
A
A
CLK
X
X
IL
n
n
; CE
X
1
and R/W = V
IH
CLK
, “L” = V
Inputs
CE
H
X
L
L
L
IL
ADS
IH
.
0
X
H
H
.
L
0
and CE
CNTEN
1
.
H
X
X
L
[24, 25, 26]
CE
H
H
H
X
L
[24, 28, 29, 30]
1
CNTRST
H
H
H
L
R/W
H
X
X
L
X
15
D
D
D
D
out(n+1)
I/O
out(0)
out(n)
out(n)
I/O
Outputs
High-Z
High-Z
High-Z
Increment
D
0
D
OUT
Mode
Reset
–I/O
Load
Hold
IN
17
Counter Reset to Address 0
Address Load into Counter
External Address Blocked—Counter
Disabled
Counter Enabled—Internal Address
Generation
Deselected
Deselected
Write
Read
Outputs Disabled
[27]
Operation
CY7C09349AV
CY7C09359AV
[27]
[27]
Operation
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